Fault Detection System Reducing Scan-Out Shift Power
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Solution Overview
Problem
Existing fault detection systems in scan tests face challenges in reducing shift power during the scan-out operation while maintaining fault coverage, as changes in test output patterns are necessary to reduce power consumption but can lead to incorrect fault detection.
Innovation Solution
A fault detection system that assigns new logic values to selected flip-flops before the final capture in the capture mode, allowing for reduced shift power during scan-out operations by selecting flip-flops based on their toggle rate, adjacency, and logic value differences, ensuring fault coverage is maintained.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If test output patterns are changed to reduce shift power during scan-out operation, then power consumption is reduced, but fault detection accuracy deteriorates
Solution Approach 1:
The patent divides the scan-out process into two segments: essential bits that must be shifted out for accurate fault detection, and non-essential bits that can be modified to reduce power consumption. By selectively applying logic values only to non-essential bits, the system reduces shift power while preserving fault detection accuracy for critical portions of the test output.
Solution Approach 2:
The patent applies different quality levels to different portions of the test output. Essential bits maintain their original captured values to ensure accurate fault detection, while non-essential bits are assigned predetermined logic values to reduce power consumption. This local differentiation allows the system to optimize power usage without compromising overall fault detection reliability.
2Loss of energy
If logic values are assigned to flip-flops before final capture, then shift power in scan-out operation is reduced, but test pattern fidelity is compromised
Solution Approach 1:
The patent performs preliminary assignment of logic values to selected flip-flops before the final capture operation. By predetermined which flip-flops will have their values assigned and ensuring they are positioned appropriately in the scan chain, the system prepares the circuit in advance to minimize power consumption during scan-out while maintaining the necessary test pattern characteristics for accurate fault detection.
Solution Approach 2:
The patent uses predetermined logic values as substitutes for the actual captured values in selected flip-flops. Instead of shifting out the actual test response values from all flip-flops, the system replaces values in selected flip-flops with predetermined logic values, creating a modified output pattern that consumes less power while still preserving the essential fault detection information.
3Reliability
If multiple captures are performed to maintain fault coverage, then fault detection accuracy is improved, but test time increases
Solution Approach 1:
The patent applies partial action by performing logic value assignment on only selected flip-flops rather than all flip-flops. By identifying and targeting specific flip-flops that are less critical for fault detection (such as those with low toggle rates or positioned in non-critical regions), the system achieves sufficient fault coverage with a single capture, thereby avoiding the time penalty of multiple captures while still maintaining adequate fault detection capability.
Data Source
AI summary
The purpose of the invention is to provide a fault detection system etc., that reduces shift power in scan-out while maintaining the fault coverage. The fault detection system configured to detect a fault in a logic circuit by means of a scan test, includes: multiple flip-flops; a final signal generation unit that generates a final signal indicating a final capture in a capture mode; an assignment unit that differs from the logic circuit and the flip-flops, and that sets a logic signal for a part of the flip-flops upon receiving the final signal; and a fault detection device that detects a fault by making a comparison between a test output captured from the logic circuit and including the logic value set by the assignment unit and a test output to be obtained when the logic circuit has no fault and including the logic value set by the assignment unit.