Fault Detection in Integrated Circuits via Time-Multiplexed Execution
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Solution Overview
Problem
Existing solutions for protecting integrated circuits against fault attacks require high hardware costs or significant memory resources, as they either use two processing devices or execute sensitive functions multiple times, leading to inefficient memory usage.
Innovation Solution
A method and device that execute a computing function twice using the same processing device and memory, with an intermediate memory device managing write and read operations to isolate and compare initial and modified parameters, allowing for fault detection without the need for redundant processing devices or excessive memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two processing devices are used to detect faults through parallel execution and comparison, then fault detection capability is improved, but hardware cost increases
Solution Approach 1:
The patent merges the functionality of two processing devices into a single processing device by implementing a time-multiplexed architecture. The same processing device executes the sensitive function multiple times with different input data sets, and the results are compared to detect faults. This eliminates the need for redundant hardware while maintaining fault detection capability.
Solution Approach 2:
The patent employs periodic execution of the sensitive function by the single processing device. The device performs multiple executions of the same function with different inputs in a sequential manner, allowing fault detection through comparison of results across these periodic executions without requiring parallel hardware.
2Reliability
If the sensitive function is executed multiple times using the same processing device, then fault detection is achieved without additional hardware, but memory resources increase
Solution Approach 1:
The patent implements a memory management strategy where intermediate results from previous executions are discarded after comparison, and memory buffers are recovered and reused for subsequent executions. Only the necessary minimal memory buffers are allocated, and they are reused across multiple executions rather than allocating separate memory spaces for each execution.
Solution Approach 2:
Instead of storing complete execution results in memory, the patent uses selective copying and comparison of critical intermediate values or checksums. This reduces the memory footprint by only storing and comparing essential verification data rather than entire execution states.
Data Source
AI summary
The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device.