Hardware Fault Detection Unit for Multi-Core Synchronization
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Solution Overview
Problem
Existing fault detection systems for safety and security applications face complexity in monitoring real-time constraints and synchronizing software tasks across multiple CPUs, often leading to resource-intensive solutions with potential deadlocks and requiring identical program codes, which can result in undetected failures if one CPU does not complete its task.
Innovation Solution
A fault detection unit comprising a comparator circuit and timer circuit that verifies data relationships between two software portions running on separate cores, signaling faults if discrepancies or timing violations occur, allowing for flexible relationship configurations and reducing the risk of deadlocks by monitoring temporal constraints in the background.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based fault detection with multiple CPUs is implemented, then fault detection capability is improved, but system complexity and resource usage increase significantly
Solution Approach 1:
A dedicated hardware comparator unit is introduced as an intermediary component between two CPUs. This comparator automatically compares outputs from both CPUs without requiring complex software synchronization mechanisms. The hardware mediator handles the comparison task efficiently, reducing the computational burden on the CPUs and simplifying the overall system architecture while maintaining fault detection capability.
Solution Approach 2:
The patent replaces software-based comparison and monitoring mechanisms with hardware-based automatic comparison circuitry. By substituting software tasks with dedicated hardware comparators and timers, the system eliminates the need for complex software synchronization, reduces CPU resource usage, and provides more reliable real-time fault detection without the overhead of software interpretation and management.
2Ease of operation
If lockstep operation with identical program codes is used, then synchronization is simplified, but fault detection accuracy decreases due to undetected common-mode failures
Solution Approach 1:
The patent allows the two CPUs to execute different program codes or different versions of the same program. Instead of requiring identical code (symmetry), the system embraces asymmetry by permitting diverse implementations. The hardware comparator then compares the outputs regardless of code identity, enabling detection of faults even when codes differ, thus improving fault detection accuracy while maintaining synchronization through output comparison rather than code identity.
3Reliability
If software monitoring tasks are implemented, then fault detection is achieved, but real-time constraint monitoring becomes difficult due to virtual time ordering
Solution Approach 1:
The patent replaces software-based time monitoring with dedicated hardware timer circuits that operate independently of software execution flow. These hardware timers provide precise real-time monitoring by generating interrupt signals when predetermined time intervals elapse, ensuring accurate timing constraints are met regardless of software scheduling or virtual time ordering. This hardware-based approach eliminates the imprecision inherent in software time management.
4Ease of operation
If synchronization mechanisms with timeout are used, then task coordination is improved, but deadlock risks increase
Solution Approach 1:
The hardware comparator acts as an intermediary that continuously monitors both CPUs without requiring them to actively coordinate or wait for each other. By passively comparing outputs as they become available, the system avoids the need for active synchronization primitives like semaphores or mutexes that can cause deadlocks. The timeout mechanism operates independently in hardware, eliminating the risk of software-based deadlock while maintaining task coordination.
Data Source
AI summary
An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.