Fault Dictionaries for IC Yield Analysis
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Solution Overview
Problem
The increasing complexity of integrated circuits due to sub-wavelength lithography leads to more frequent feature-related defects, making it costly and inefficient to use test chips for determining design manufacturing rules, which are essential for improving production yield, as they require frequent updates and provide limited information.
Innovation Solution
A method that extracts potential defects from integrated circuit designs using derived defect extraction rules, applies circuit tests to identify failing circuits, analyzes test responses to determine defect likelihood, and updates defect extraction rules based on collected information to improve yield and reduce the need for test chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test chips are used to determine design manufacturing rules, then design manufacturing rules can be established, but the cost and time consumption increase significantly
Solution Approach 1:
The patent creates a virtual model (fault dictionary) that copies and simulates the behavior of physical test chips. This virtual model allows designers to evaluate design manufacturing rules and predict defect patterns without physically manufacturing and testing actual test chips, thereby eliminating the time-consuming iterative process of chip fabrication and testing while maintaining the accuracy of rule determination
Solution Approach 2:
The fault dictionary is constructed in advance by simulating various defect scenarios and storing the expected test responses. This preliminary action allows the system to immediately compare actual test results against pre-computed fault patterns, eliminating the need for time-consuming real-time analysis and enabling rapid determination of design manufacturing rules
2Reliability
If test chips are used to determine design manufacturing rules, then design manufacturing rules can be established, but the cost increases significantly
Solution Approach 1:
The patent replaces expensive physical test chips with a computational fault dictionary that simulates their function. By using software-based defect simulation and test response prediction, the system eliminates the need to manufacture, ship, and physically test expensive test chips, thereby dramatically reducing costs while maintaining the ability to establish accurate design manufacturing rules
Solution Approach 2:
The patent substitutes the mechanical/physical system of actual test chip manufacturing and testing with a computational system. Instead of physically creating test structures and measuring their behavior, the system uses algorithms to simulate defect patterns and predict test outcomes, replacing costly physical processes with efficient computational methods
3Loss of information
If traditional test chips are used, then limited defect information can be obtained, but new test chips must be designed and manufactured for each new DFM rule
Solution Approach 1:
The fault dictionary is designed to be dynamic and adaptable. When new design manufacturing rules are introduced or process changes occur, the system can update the fault dictionary by re-simulating defect patterns according to the new rules without requiring physical chip redesign. This dynamic updating capability enables rapid adaptation to new requirements while maintaining comprehensive defect information coverage
Solution Approach 2:
The fault dictionary serves multiple functions: it can evaluate existing design manufacturing rules, predict defect patterns for new rules, and adapt to process changes. This multi-functionality eliminates the need to create separate test chips for each DFM rule evaluation, allowing a single flexible system to handle diverse rule sets and defect scenarios
Data Source
AI summary
Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.