Fault-Driven Scan Chain Partitioning for Test-Per-Clock

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Solution Overview

Problem

Existing scan-based testing methods, such as test-per-scan and conventional test-per-clock BIST schemes, are inefficient in terms of testing time and power consumption, with a significant portion of time spent on data shifting and excessive circuit toggling leading to high power dissipation.

Innovation Solution

The implementation of fault-driven techniques to dynamically partition and reconfigure scan chains, allowing them to operate in different modes for testing, such as shifting-launching, capturing-compacting-shifting, and mission modes, to optimize fault detection and response compaction, reducing unnecessary shifting and power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If test-per-scan scheme is used, then test patterns can be applied to circuit-under-test, but test time is significantly increased due to slow shifting operations

Engineering Contradiction:
Improvetest qualityVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments scan chains into different groups (first group for pattern loading, second group for response capturing) and assigns different operational modes to each group. This segmentation allows simultaneous pattern application and response capture, eliminating the sequential shifting bottleneck in traditional test-per-scan methods.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically reconfigures scan chain operational modes during testing. Scan chains can switch between shift mode, capture mode, and compact mode based on test requirements. This dynamic reconfiguration enables test-per-clock operation where patterns are applied and responses captured at full circuit clock frequency rather than slow shift frequency.

Inventive Principle:
Principle #15Dynamics

2Productivity

If conventional BIST test-per-clock scheme is used, then test time efficiency is improved, but power consumption increases due to excessive circuit toggling

Engineering Contradiction:
Improvetest time efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies different operational characteristics to different scan chain groups. The first group operates in shift mode with controlled toggling for pattern loading, while the second group operates in capture/compact mode with minimized toggling for response collection. This local differentiation reduces overall circuit toggling and power consumption compared to uniform operation of all scan chains.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements periodic reconfiguration of scan chain modes in a test-per-clock scheme. Scan chains alternately perform shifting, capturing, and compaction operations in structured phases. This periodic action allows efficient test execution while controlling power consumption through rhythmic, predictable toggling patterns rather than continuous random toggling.

Inventive Principle:
Principle #19Periodic action

3Reliability

If scan chains are reconfigured for different testing modes, then fault detection capability is improved, but device complexity increases

Engineering Contradiction:
Improvefault detection capabilityVSAvoidscan chain configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs scan chains to be multi-functional, capable of operating in shift mode, capture mode, and compact mode. The same physical scan chain infrastructure serves multiple testing purposes through reconfiguration. This universality improves fault detection capability without proportionally increasing hardware complexity, as the same resources are flexibly allocated rather than duplicating structures for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9003248B2Fault-driven scan chain configuration for test-per-clock
Publication Date: 2015.04.07 SIEMENS INDUSTRY SOFTWARE INC
  • US9003248B2 patent drawing
  • US9003248B2 patent drawing
  • US9003248B2 patent drawing

AI summary

Aspects of the invention relate to using fault-driven techniques to generate scan chain configurations for test-per-clock. A plurality of test cubes that detect a plurality of faults are first generated. Scan chains for loading specified bits of the test cubes are then assigned to a stimuli group. From the plurality of test cubes, a test cube that detects a large number of faults that do not propagate exclusively to scan chains in the stimuli group is selected. One or more scan chains that are not in the stimuli group and are needed for observing the large number of faults are assigned to a compacting group. The number of scan chains either in the compacting group or in both of the compacting group and the stimuli group may be limited to a predetermined number.