Fault Injection Reduction in Functional Safety Gate Netlists
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Solution Overview
Problem
Current fault injection techniques for electronic circuits are time-consuming, computationally intensive, and lack automated methods to identify and eliminate redundant sub-circuits, leading to inaccurate diagnostic coverage and inefficient use of computing resources.
Innovation Solution
An automated methodology using sub-graph isomorphism and toggle coverage equivalence to identify and eliminate duplicate sub-circuits after synthesis, reducing the fault injection list and maintaining diagnostic coverage accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complete fault list is used for fault injection simulation, then diagnostic coverage accuracy is improved, but computing time and resources are excessively consumed
Solution Approach 1:
The circuit design is divided into sub-circuits, and the fault list is segmented accordingly. By identifying and eliminating duplicate sub-circuits through sub-graph isomorphism, the fault injection simulation processes only unique sub-circuits, significantly reducing computing time while maintaining diagnostic coverage accuracy through systematic segmentation and analysis of circuit components
Solution Approach 2:
The patent uses graph representations (copies) of circuit sub-circuits to identify duplicates. By creating and comparing graph models of sub-circuits, the system can efficiently identify identical structures without re-simulating them multiple times, reducing computational overhead while preserving the complete diagnostic coverage that would be obtained from analyzing all original instances
2Reliability
If fault injection simulation is performed on all sub-circuits, then comprehensive diagnostic coverage is achieved, but computing resources are wasted on redundant simulations
Solution Approach 1:
The circuit is segmented into sub-circuits that are represented as graphs. By comparing these graph representations, duplicate sub-circuits are identified and eliminated from the simulation list. This segmentation approach ensures that computing resources are allocated only to unique sub-circuits, preventing waste on redundant simulations while maintaining comprehensive diagnostic coverage through systematic analysis of all unique circuit components
Solution Approach 2:
The patent transforms the circuit representation into graph parameters (nodes, edges, connectivity) that enable efficient comparison and identification of duplicate sub-circuits. By changing the representation parameters from traditional circuit diagrams to graph structures with specific attributes, the system can quickly identify duplicates using sub-graph isomorphism algorithms, reducing computational resource consumption while preserving diagnostic integrity
3Loss of energy
If manual identification of duplicate sub-circuits is performed, then redundant simulations are eliminated, but automation and efficiency are reduced
Solution Approach 1:
The patent replaces manual visual inspection and identification of duplicate sub-circuits with automated graph-based algorithms. By substituting the mechanical/manual process with computational sub-graph isomorphism detection, the system achieves both high automation and computing resource efficiency. The automated graph comparison algorithms systematically identify duplicate sub-circuits without human intervention, eliminating the trade-off between automation extent and resource efficiency
Data Source
AI summary
Techniques are disclosed for eliminating redundancy in fault simulations to improve efficiency and to reduce the time and computing power required to generate a robust fault list, which results in adequate diagnostic coverage of a particular post-silicon electronic device for functional safety applications. The techniques described herein implement an automated methodology to identify identical sub-circuits in a design after the design is synthesized to gates, and utilize isomorphism to define a manner in which identical blocks may be reliably identified to ensure adequate coverage and accurate, consistent fault injection results. The netlist may advantageously implement a “flat” as opposed to a hierarchal design. Moreover, multiple levels of granularity may be identified for the various sub-circuits associated with the reference graphs used to identify isomorphic sub-graphs.


