Electronic Device Fault Injection Detection Through Flip-Flop Timing Checks
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Solution Overview
Problem
Existing electronic devices face challenges in efficiently and reliably detecting fault injection attacks, particularly due to their localized nature and the need for cost-effective, low-power solutions that can be integrated into existing systems.
Innovation Solution
An electronic device equipped with distributed detectors, such as D flip-flops, monitors power supply and clock periods, using a comparator to evaluate timing violations caused by fault injections, allowing for efficient and reliable detection of set-up and hold violations without requiring analog changes or significant power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distributed detectors are used to detect localized fault injection attacks, then detection coverage and reliability are improved, but device complexity increases
Solution Approach 1:
The electronic device is divided into multiple segments, each with its own detector monitoring local power supply and clock signals. This segmentation enables detection of localized fault injection attacks while keeping each detector module simple and modular, thus improving overall detection reliability without excessive complexity increase.
Solution Approach 2:
The detectors are designed as universal multi-functional units that monitor both power supply voltage and clock signals simultaneously. Each detector can detect multiple types of fault injection attacks (power glitches, electromagnetic pulses, temperature variations) using the same hardware structure, improving reliability while avoiding the complexity of multiple specialized detectors.
2Reliability
If a detector monitors power supply and clock period to detect fault injection attacks, then detection capability is improved, but power consumption increases
Solution Approach 1:
The detector performs periodic sampling of power supply voltage and clock period rather than continuous monitoring. By checking these parameters at specific intervals synchronized with clock edges, the detector maintains high detection capability for fault injection attacks while significantly reducing average power consumption compared to continuous monitoring.
Solution Approach 2:
The detector utilizes existing clock signals and power supply rails within the electronic device for its operation, rather than requiring separate dedicated power sources or signal generators. The detector self-services by borrowing timing references and voltage levels from the device's own operating signals, minimizing additional power consumption while maintaining detection capability.
3Ease of manufacture
If digital implementation is used for fault injection detection, then ease of integration and cost-effectiveness are improved, but measurement precision may be reduced
Solution Approach 1:
The patent replaces analog measurement systems with digital implementation. Instead of using analog voltmeters and oscilloscopes to monitor power supply and clock signals, the detector uses digital logic circuits that sample and compare these signals against predefined thresholds. This substitution dramatically improves ease of integration into existing digital devices and reduces cost, while maintaining sufficient precision through carefully chosen threshold values and sampling strategies.
Data Source
AI summary
A fault detection circuit can detect setup time and/or hold time faults which can indicate a possible fault injection attack using flip-flop circuits which are powered by a supply voltage and receive a clock signal. A hold time violation can be identified by providing the clock signal to a data input of a D flip-flop or equivalent circuit, and the complement of the clock signal, with a predetermined delay to clock input of the flip-flop. The hold time violation is indicated when the inverted and delayed clock signal has a different voltage from the uninverted (and undelayed) clock signal. Setup time violations can be identified by connecting the inverted output of each of a pair of flip-flops to their respective data input terminals in a feedback arrangement. For one of the flip flops, the feedback loop includes a predetermined delay. A setup time fault is indicated when the output voltages of the two flip-flops are different from each other.