Fault Injection Verification for Functional Safety Coverage

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Solution Overview

Problem

Current design verification methods for electronic systems, especially in the automotive sector, fail to adequately address functional safety issues and external fault scenarios, such as radiation and physical trauma, which can lead to unexpected states and safety risks, beyond mere functional bugs.

Innovation Solution

A method for functional safety verification that involves obtaining and analyzing a set of verification tests, injecting faults into the design under test (DUT), and performing test ordering based on a hierarchy tree representation to identify and prioritize fault clusters, using techniques like toggle coverage and user-defined percentages to optimize test execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fault injection is performed on all verification tests to ensure comprehensive safety verification, then functional safety coverage is improved, but verification time and computational resources increase significantly

Engineering Contradiction:
Improvefunctional safety coverageVSAvoidverification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the verification process by clustering faults into groups based on their location in the hierarchy tree and similarity in behavior. Instead of treating all faults independently, related faults are grouped together, allowing the system to analyze and verify safety properties more efficiently by processing fault clusters rather than individual faults, thus reducing verification time while maintaining comprehensive safety coverage

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by selectively analyzing fault clusters based on their risk levels and importance. Not all faults require the same level of verification attention, so the system prioritizes fault clusters that pose higher safety risks while potentially reducing verification intensity for lower-risk faults, thereby optimizing the balance between safety coverage and verification time

Inventive Principle:
Principle #16Partial or excessive action

2Measurement precision

If all verification tests are executed to detect every possible fault, then detection precision is improved, but device complexity and testing overhead increase

Engineering Contradiction:
Improvefault detection precisionVSAvoidtesting overhead
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments faults into clusters based on their hierarchical location and characteristics, allowing the verification system to focus on specific fault groups rather than treating all faults uniformly. This segmentation enables precise detection of critical faults while reducing the overall testing overhead by excluding less critical faults from intensive verification procedures

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by assigning different verification intensities to different fault clusters based on their specific characteristics and risk levels. Fault clusters in critical areas receive more intensive testing and analysis, while fault clusters in less critical areas undergo simplified verification, thereby maintaining high detection precision for important faults while reducing overall testing overhead

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10540461B1Method and system for functional safety verification
Publication Date: 2020.01.21 CADENCE DESIGN SYST INC
  • US10540461B1 patent drawing
  • US10540461B1 patent drawing
  • US10540461B1 patent drawing

AI summary

A method for functional safety verification for use in a verification of a design under test (DUT), includes obtaining a set of verification tests previously executed on the DUT and related execution data; injecting a fault into each of the tests of the set of verification tests; analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree; and for each of the clusters of faults, based on the execution data, performing test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located.