Fault Insertion in Compiled Electronic Circuit Design
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Solution Overview
Problem
Automobile manufacturers face challenges in ensuring the safety and reliability of electronic components due to the limitations of conventional electrical testing methods, which are costly and time-consuming, and cannot cover all possible fault conditions effectively.
Innovation Solution
A computer-implemented method and system that allows for the modification of a compiled electronic circuit design without recompilation, enabling robust fault simulation by generating a modified version of the design in response to changes, thereby simulating different types of faults and understanding their impact before physical prototypes are built.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electrical testing methods are used to verify electronic components, then reliability assessment can be achieved, but the process becomes costly and time-consuming
Solution Approach 1:
The patent applies preliminary action by performing fault simulation during the design phase before physical prototypes are built. The system inserts fault elements into the design description and simulates their effects computationally, allowing reliability assessment to be conducted in advance without requiring actual physical testing, thereby saving time while maintaining reliability evaluation capability
Solution Approach 2:
The patent uses copying by creating virtual copies of the electronic system through compilation of design descriptions into simulated systems. These compiled representations serve as digital twins that can be tested extensively for various fault conditions without affecting physical hardware, enabling rapid reliability assessment without time-consuming physical testing
2Adaptability or versatility
If conventional fault simulators are used to introduce fault elements, then fault simulation capability is provided, but every design change requires time-consuming recompilation
Solution Approach 1:
The system performs preliminary compilation of the design description into a simulated system before fault insertion. This pre-compiled base system can then be efficiently modified by adding fault elements without requiring complete recompilation, thus maintaining high simulation efficiency while supporting multiple fault types and design changes
Solution Approach 2:
The patent segments the compilation process into a base system compilation phase and a fault insertion phase. The design description is first compiled into a base simulated system, then fault elements are inserted as separate modifications. This segmentation allows the base system to be compiled once and reused across multiple fault simulation scenarios, dramatically improving productivity while maintaining comprehensive fault simulation capability
3Reliability
If comprehensive electrical testing is performed to cover all fault conditions, then system safety can be verified, but the testing process becomes extremely costly
Solution Approach 1:
The patent creates compiled simulated systems that serve as virtual copies of the physical electronic system. These digital replicas can be tested extensively for all possible fault conditions without consuming physical testing resources. The simulation environment allows unlimited fault injection and scenario testing at minimal cost while maintaining the ability to verify system safety comprehensively
Solution Approach 2:
The patent uses computational fault simulations as inexpensive alternatives to costly physical testing. Each fault simulation scenario can be executed virtually without consuming durable physical resources, allowing comprehensive safety verification across numerous fault conditions at minimal resource expenditure compared to traditional electrical testing methods
Data Source
AI summary
A computer implemented method of modifying a compiled design of an electronic circuit is disclosed. The method includes accessing a stored compilation representing the design, and causing the computer to generate a modified version of the stored compilation in response to an indication of a change to a portion of the design.