Fault Insertion Device for MIL-STD-1553 Bus Testing
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Solution Overview
Problem
Testing of MIL-STD-1553/1760 control and communications systems in aircraft and spacecraft is challenging due to timing requirements, making it difficult to selectively introduce communications faults to simulate failure conditions.
Innovation Solution
A fault insertion device (FID) is integrated into the system, comprising a transceiver and a field-programmable gate array (FPGA) that evaluates and modifies messages on the MIL-STD-1553/1760 bus in real-time, allowing for selective introduction of faults based on bus traffic patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fault insertion device is integrated into the MIL-STD-1553/1760 communications bus, then selective fault introduction capability is improved, but device complexity increases
Solution Approach 1:
The patent implements a fault insertion device (FID) that acts as an intermediary component integrated into the MIL-STD-1553/1760 communications bus. The FID includes a transceiver for receiving and transmitting signals along the bus, and an FPGA that processes the signals. This intermediary structure enables selective fault introduction by monitoring bus traffic and injecting faults only when specific conditions are met, thereby improving adaptability while containing complexity through modular design.
Solution Approach 2:
The patent employs dynamic fault insertion based on real-time bus traffic analysis. The FPGA evaluates received signals against programmed rules and selectively modifies or blocks signals based on current bus conditions. This dynamic approach allows the system to adapt fault insertion behavior to varying operational contexts, improving versatility while managing complexity through rule-based decision logic rather than continuous monitoring and intervention.
2Measurement precision
If real-time message evaluation and modification is performed, then fault simulation accuracy is improved, but processing time increases
Solution Approach 1:
The patent implements preliminary action by pre-programming the FPGA with a set of rules that define fault insertion conditions. These rules are established before the fault insertion process begins, allowing the FPGA to quickly evaluate incoming signals against predetermined criteria rather than performing complex analysis in real-time. This preliminary configuration enables accurate fault simulation while minimizing processing delay.
Solution Approach 2:
The patent replaces complex software-based real-time analysis with hardware-based FPGA processing. The FPGA's parallel architecture and dedicated logic circuits enable simultaneous evaluation of multiple bus traffic patterns and rapid decision-making about fault insertion. This hardware substitution eliminates the need for time-consuming software processing while maintaining high accuracy in fault simulation, as the FPGA can evaluate signals at the bit level with minimal latency.
Data Source
AI summary
A fault insertion device (FID) comprises a transceiver and an FPGA. The transceiver receives signals from a MIL-STD-1553/1760 communications bus. The FPGA evaluates the signals received from the communications bus against a set of rules stored by the FPGA. Based upon the set of rules, the FPGA can selectively modify messages received from the communications bus prior to transmission to a remote terminal or a bus controller that is configured to communicate on the communications bus.