Fault Logic Circuit for Accurate Power Fault Sequence Recording
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Solution Overview
Problem
Existing fault sequence recording systems in enterprise server systems struggle to accurately record and store the sequence of events leading up to a system shutdown caused by a power fault, due to latency issues in digital bus interfaces, which makes troubleshooting and failure analysis difficult.
Innovation Solution
A fault monitoring system comprising a fault logic circuit, a write control circuit, a timer, and a data register, which compares sensor data values to fault thresholds, records event information and time stamps for each fault event in a fault register, and stores this information in a nonvolatile memory for later analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a digital bus interface is used to record fault sequence data, then data transmission capability is improved, but latency increases making accurate sequence recording difficult
Solution Approach 1:
The patent extracts the critical timing information and fault sequence data directly from the digital bus interface before latency occurs. By using a dedicated fault recording mechanism that captures data at the source (sensor inputs and bus signals) rather than relying on post-processing of delayed data, the system preserves accurate temporal sequence information despite the inherent latency of digital communication buses.
Solution Approach 2:
The system performs preliminary recording of fault events and timing information as they occur on the digital bus interface. The fault recording mechanism proactively captures data values, fault thresholds, and temporal information before the complete data transmission cycle finishes, ensuring that the sequence of events is recorded accurately despite subsequent latency in full data processing.
2Measurement precision
If fault sequence data is recorded in real-time, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the fault recording function into distinct modular components: sensor input interfaces, fault threshold comparison logic, timing measurement circuits, and data storage elements. Each component handles a specific aspect of the recording process independently, allowing real-time precise recording while keeping individual module complexity manageable and enabling easier design and maintenance.
Solution Approach 2:
The fault recording mechanism is designed to handle multiple types of fault conditions and data formats through a unified approach. The same recording infrastructure processes different sensor inputs, fault thresholds, and event types, reducing overall system complexity compared to having separate specialized recording circuits for each fault type while maintaining high measurement precision across all recorded events.
Data Source
AI summary
Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.