Fault Logic Circuit for High-Resolution Event Recording

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Solution Overview

Problem

Existing fault sequence recording systems in enterprise server systems struggle to accurately record and reconstruct the sequence of events leading up to a system shutdown caused by a power fault, due to latency issues and limited time resolution.

Innovation Solution

A fault monitoring system comprising a fault logic circuit, a write control circuit, a timer, and a data register, which compares sensor data values to fault thresholds, records fault events with associated timing information, and stores this data in a nonvolatile memory for later analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a fault sequence recording system is implemented using conventional methods, then fault events can be recorded, but the time resolution and accuracy of the recorded sequence are insufficient due to latency issues

Engineering Contradiction:
Improvetime resolutionVSAvoidlatency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-configuring multiple fault types and their corresponding thresholds before faults occur. The system continuously monitors parameters against pre-set thresholds and prepares recording mechanisms in advance, enabling immediate capture of fault events without processing delays when faults actually occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the fault recording system into distinct functional modules: parameter monitoring units for different system parameters, threshold comparison units for different fault types, and a centralized recording unit. This segmentation allows parallel processing of multiple parameters simultaneously, improving time resolution by eliminating sequential processing bottlenecks.

Inventive Principle:
Principle #1Segmentation

2Loss of information

If detailed fault event information is recorded for every fault event, then debugging and failure analysis capability is improved, but the complexity of the recording system increases

Engineering Contradiction:
Improvefault event information completenessVSAvoidrecording system complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent implements a universal recording structure where a single recording unit handles multiple fault types by receiving standardized fault indicators from different parameter monitoring units. Each fault event is recorded using a common format including timestamp, fault type identifier, and parameter values, allowing the system to capture diverse fault information without requiring separate complex recording mechanisms for each fault type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the system continuously monitors and records all parameter changes, then fault detection capability is improved, but the energy consumption and processing load increase

Engineering Contradiction:
Improvefault detection capabilityVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by assigning different monitoring thresholds and recording priorities to different system parameters based on their criticality. Critical parameters with higher fault risk are monitored continuously with lower thresholds, while less critical parameters use higher thresholds and less frequent monitoring. This selective approach maintains high fault detection capability for critical issues while reducing overall energy consumption and processing load.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12235319B2System and method for fault sequence recording
Publication Date: 2025.02.25 TEXAS INSTRUMENTS INC
  • US12235319B2 patent drawing
  • US12235319B2 patent drawing
  • US12235319B2 patent drawing

AI summary

Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.