Fault-Mitigating Data Processing Circuit for Neural Network Memory
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Solution Overview
Problem
Faulty bits in memory storage for neural networks, particularly in convolutional neural networks, significantly affect image recognition accuracy, leading to reduced success rates even with higher bit errors.
Innovation Solution
A data processing circuit and fault-mitigating method that ignore faulty bits in memory and replace their values with non-faulty bits, ensuring accurate data processing for image recognition by using a controller to manage data access and replacement within the memory, maintaining acceptable accuracy even with higher bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If faulty bits in memory are accessed for data storage, then memory capacity is fully utilized, but image recognition accuracy deteriorates significantly
Solution Approach 1:
The patent extracts and removes faulty bits from the memory access sequence by using a mapping mechanism that skips defective locations. The controller identifies faulty bit positions and creates a mapping table that redirects access to valid bits only, effectively separating problematic elements from the functional system.
Solution Approach 2:
The patent introduces a mapping table as an intermediary layer between the controller and physical memory bits. This mapping table translates logical memory addresses to physical bit positions, allowing the system to access memory while automatically avoiding faulty bits through the intermediary translation layer.
2Measurement precision
If faulty bits are replaced with non-faulty bit values, then image recognition accuracy is improved, but data processing complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-identifying faulty bits during a testing phase and creating a mapping table in advance. This pre-processing step stores the faulty bit positions and corresponding replacement values, so that during actual data processing, the system can directly apply the pre-computed corrections without complex real-time analysis.
Solution Approach 2:
The system performs self-service by automatically detecting, mapping, and correcting faulty bit access without external intervention. The controller autonomously manages the mapping table and applies corrections during memory access operations, making the fault mitigation process transparent and self-contained.
3Reliability
If a mapping table is used to skip faulty bits, then access to faulty bits is avoided, but memory access time increases
Solution Approach 1:
The patent applies asymmetry by creating a non-uniform mapping where consecutive logical addresses do not necessarily map to consecutive physical bit positions. The mapping table uses asymmetric indexing and stride calculations to skip faulty bits efficiently, allowing variable-step access patterns that optimize for reliability while minimizing time loss through mathematical optimization.
Data Source
AI summary
A data processing circuit and a fault-mitigating method, which are adapted for a memory having a faulty bit, are provided. The memory is configured to store data related to an image, a weight for a multiply-accumulate (MAC) operation of image feature extraction, and/or a value for an activation operation. Sequence data is written into the memory. The bit number of the sequence data equals to the bit number used for storing data in a sequence block of the memory. The sequence data is accessed from the memory, wherein the access of the faulty bit in the memory is ignored. The value of the faulty bit is replaced by the value of a non-faulty bit in the memory to form new sequence data. The new sequence data is used for MAC. Accordingly, the accuracy of image recognition can be improved for the faulty memory.