Fault Node Grouping for Integrated Circuit Hardware Design Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for fault injection testing of integrated circuit hardware designs are time-consuming, expensive, and difficult to debug, especially for complex designs like GPUs, due to the high number of fault nodes and limited resources, leading to impractical testing of all possible fault nodes.
Innovation Solution
The method involves grouping fault nodes into fault node groups based on their effect on failure modes and selecting nodes for injection tests based on these groups, reducing the number of tests required to ensure thorough fault injection testing, using simulation-based approaches to mimic real-world fault occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault injection testing is performed on all fault nodes in complex integrated circuit designs, then testing thoroughness is improved, but testing time and computational resources are excessively consumed
Solution Approach 1:
The patent segments the large set of fault nodes into multiple groups based on their effects on failure modes. This segmentation allows the testing process to focus on representative fault nodes from each group rather than testing all fault nodes individually, thereby reducing testing time while maintaining comprehensive coverage of all failure modes.
Solution Approach 2:
The patent applies partial action by selecting and testing only a subset of fault nodes that are most representative of each failure mode group. This partial testing approach is sufficient to validate the safety mechanisms for all failure modes without requiring exhaustive testing of every single fault node, thus achieving thoroughness with reduced time investment.
2Reliability
If fault injection testing is performed on all fault nodes in complex integrated circuit designs, then testing thoroughness is improved, but computational resources are excessively consumed
Solution Approach 1:
By segmenting fault nodes into groups based on their effects on failure modes, the patent reduces the computational burden. Instead of performing fault injection tests on every fault node, the system tests representative nodes from each segment, significantly improving computational resource efficiency while maintaining comprehensive validation of safety mechanisms.
Solution Approach 2:
The patent performs partial testing by selecting only the necessary subset of fault nodes required to validate each failure mode group. This approach achieves sufficient testing thoroughness without the excessive computational resource consumption that would result from testing all fault nodes, thereby improving productivity.
3Measurement precision
If fault injection testing is performed in silicon or FPGA to mimic real-world fault occurrences, then test accuracy is improved, but debugging difficulty and cost increase
Solution Approach 1:
The patent creates a virtual copy of the integrated circuit design at the gate-level simulation stage and performs fault injection testing on this copy. This copying approach allows accurate simulation of real-world fault occurrences without the debugging difficulties and high costs associated with physical silicon or FPGA testing, while still maintaining sufficient test accuracy to validate safety mechanisms.
Data Source
AI summary
Methods and systems for performing fault injection testing on an integrated circuit hardware design. The methods include: (a) receiving a raw fault node list identifying one or more fault nodes of the hardware design; (b) receiving information indicating a grouping of the fault nodes in the raw fault node list into a plurality of fault node groups, each fault node group comprising fault nodes that have a same effect on a failure mode of the hardware design; (c) generating a final fault node list based on the fault node groups; (d) selecting a set of fault injection parameters from the final fault node list, the set of fault injection parameters identifying at least one fault node in the final fault node list to fault; (e) performing a fault injection test on the hardware design by causing a fault to be injected into a simulation of the hardware design based on the selected set of fault injection parameters; (f) determining a result of the fault injection test; (g) storing the result of the fault injection test; and repeating (d) to (g) at least once.