Integrated Fault Output Delay Circuit for Noise-Immune Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed fault detection in electronic applications is challenging due to noise issues, which can lead to erroneous fault indications, and existing solutions require multiple pins to set delay periods, increasing package size and reducing functionality.
Innovation Solution
A time delay fault device using a single pin of an integrated circuit, incorporating a field effect transistor, latch, and comparator with an external resistor-capacitor network to set a user-definable delay period for the fault indication signal, allowing for accurate fault detection without introducing errors from noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If filtering techniques are used to reduce noise, then noise reduction is improved, but fault detection speed deteriorates
Solution Approach 1:
A time delay circuit is introduced as an intermediary component between the fault detection circuit and the output. This circuit uses an RC network to provide a predetermined time delay that filters out transient noise while allowing genuine faults to be detected, thus reducing noise without significantly impacting fault detection speed
2Adaptability or versatility
If multiple pins are used for fault indication and delay setting, then functionality is improved, but package size and die area increase
Solution Approach 1:
The fault indication output and the delay setting function are merged into a single pin of the integrated circuit. The same pin that provides the delayed fault indication signal also accepts the external capacitor that sets the delay period, thereby reducing pin count and allowing for smaller package size and die area
Solution Approach 2:
A single pin is designed to serve multiple functions: it outputs the delayed fault indication signal and simultaneously accepts the external capacitor connection for setting the time delay. This multi-functional design reduces the overall pin count required for the integrated circuit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces erroneous fault indications by introducing a time delay that compensates for noise phenomena, allowing for accurate fault detection using a single pin, thereby enhancing fault detection capabilities while minimizing package size and die area.
Implementation Method 1
the time delay circuit is responsive to an external reference signal from a resistor capacitor network coupled to the delayed fault indicator signal output to set the time delay
Implementation Method 2
the time delay circuit includes a field effect transistor having a gate, a drain connected to ground, and a source connected to the output of the time delay circuit
Implementation Method 3
a comparator having an output connected the input of the latch and a first and a second input, the first input connected to an internal reference signal and the second input connected to the output of the time delay circuit
Data Source
AI summary
A time delay fault device includes an integrated circuit (IC) having an electronic circuit having a fault indicator signal output and a time delay circuit having an input connected to the fault indicator signal output and an output to provide a delayed fault indicator signal output, the time delay circuit being responsive to an external voltage from a resistor capacitor network coupled to the delayed fault indicator signal output to set the time delay of the delayed fault indicator signal.