Functional Safety Verification Using Fault Relation Rules
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Solution Overview
Problem
Current functional safety verification processes for electronic designs are tedious and time-consuming, requiring extensive checks across millions of gates in electronic circuits to ensure that faults are detectable, especially in sequential logic elements, which limits efficiency and compliance with industry standards like ISO 26262.
Innovation Solution
A computer-implemented method and system that simulate stuck-at faults in sequential elements of electronic designs, applying fault relation rules to determine detectability by safety mechanisms at output and input ports, reducing the number of checks needed by identifying equivalent and dominant fault relations, and calculating diagnostic coverage grades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive checks are performed across all points in electronic design to verify fault detectability, then functional safety compliance is ensured, but verification time and computational resources increase significantly
Solution Approach 1:
The verification process is segmented into two phases: first verifying output ports of sequential elements, then using fault relation rules to determine which input ports require verification. This segmentation reduces the total number of points that need explicit checking while maintaining comprehensive safety coverage.
Solution Approach 2:
The method performs preliminary verification at output ports first, then uses the results to predict which input ports need verification through fault relation rules. This preliminary action at output ports enables subsequent reduction of input port verification requirements, saving time in the overall process.
2Productivity
If fault relation rules are applied to reduce the number of check points, then verification efficiency improves, but the complexity of the verification method increases
Solution Approach 1:
Fault relation rules serve as an intermediary mechanism that connects output port verification results to input port verification requirements. These rules act as a mediator that automatically determines which input ports need checking based on output port results, reducing manual analysis complexity while improving efficiency.
Solution Approach 2:
The method uses fault relation rules to create a simplified representation of fault propagation relationships. Instead of verifying every possible fault scenario directly, the rules copy and transfer verification requirements from output ports to relevant input ports, reducing the verification burden while maintaining accuracy.
3Reliability
If all input ports of sequential elements are verified for fault detectability, then complete safety coverage is achieved, but the number of simulation runs and computational resources required increase
Solution Approach 1:
The verification approach applies local quality by treating different input ports differently based on their fault detectability characteristics. Instead of uniformly verifying all input ports, the method identifies and verifies only those input ports that are actually reachable and detectable, allocating computational resources efficiently to high-priority verification points.
Solution Approach 2:
The method performs partial verification of input ports by using fault relation rules to identify only the necessary subset of input ports that require verification. This partial action is sufficient to achieve complete safety coverage because the rules ensure that all detectable faults are covered, eliminating unnecessary verification of redundant points.
Data Source
AI summary
A computer implemented method for functional safety verification includes simulating SA0 and/or SA1 faults at a Q output port of each sequential element in a first representation of an electronic design, to determine whether any of the simulated faults is detectable by a safety mechanism, determining, based on one or more fault relation rules and based on a second gate-level representation of the electronic design, whether any of the faults is also detectable by the safety mechanism if occurred at one or more input ports of the respective sequential element or one or more input ports of a clockgate of the respective sequential element, and identifying a remainder of input ports and input ports of a clockgate of each of the sequential elements at which the faults are not determined to be detectable by the safety mechanism based on the one or a plurality of fault relation rules.