Fault Resilient Apparatus Using Compare Data Blocks
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Solution Overview
Problem
Current fault detection methods in data processing systems, such as Dual-Core-Lock-Step (DCLS), require duplicating processor components to achieve high fault detection coverage, leading to significant area and power overhead, which is undesirable in modern systems with increasing performance and features.
Innovation Solution
An apparatus with storage and processing circuitry that performs match condition indications for compare data blocks, and evaluation circuitry to check for false hits, allowing for robust fault detection without duplicating processing circuitry, thereby reducing power and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spatial redundancy such as Dual-Core-Lock-Step (DCLS) is used to achieve high fault detection coverage, then reliability is improved, but area and power consumption increase significantly
Solution Approach 1:
The processor core is segmented into functional units (ALU, register file, control logic) that can be selectively replicated. Only critical path components are duplicated for fault detection, while non-critical components share resources, reducing overall area overhead while maintaining reliability.
Solution Approach 2:
The redundant processing circuitry is designed to serve multiple functions: normal data processing, fault detection through comparison, and error correction. The same hardware structures are used for both computation and verification, eliminating the need for completely separate redundant systems and reducing area consumption.
2Reliability
If spatial redundancy such as Dual-Core-Lock-Step (DCLS) is used to achieve high fault detection coverage, then reliability is improved, but power consumption increases significantly
Solution Approach 1:
The fault detection mechanism operates periodically by enabling comparison logic only during critical operations or at scheduled intervals rather than continuously. The redundant circuitry is activated in sync with the primary core during lock-step operation and can be deactivated during non-critical periods, reducing average power consumption while maintaining fault detection capability.
Solution Approach 2:
Power management is applied locally to different functional units based on their fault-criticality. Highly critical components maintain full redundant operation, while less critical components use reduced redundancy or on-demand activation, optimizing the balance between reliability and power consumption across different parts of the system.
3Reliability
If combinational circuitry is duplicated for table lookup and address decoding functions, then fault detection coverage is improved, but area and power consumption penalties increase
Solution Approach 1:
The combinational logic for table lookup and address decoding is merged between redundant instances. Shared read-only memory structures are used for lookup tables, and common control logic is replicated only where necessary for fault detection. This merging approach maintains fault detection coverage by keeping critical paths separate while sharing non-critical resources, thereby reducing area and complexity.
Data Source
AI summary
An apparatus for providing fault resilience has storage for providing a plurality of compare data blocks, and processing circuitry that performs, for each compare data block, a processing operation using the input data and the compare data block to produce a match condition indication for that compare data block. Performance of the processing operation for each compare data block should result in only one match condition indication indicating a match. Evaluation circuitry evaluates the match condition indications produced for the plurality of compare data blocks and is arranged, in the presence of only one match condition indication indicating a match, to perform a false hit check procedure in order to check for presence of a false hit. In the presence of the false hit, the evaluation circuitry produces an error indication as the outcome indication, but otherwise produces a hit indication as the outcome indication.