Fault Resistant Verification Data Processor
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Solution Overview
Problem
Existing data processing systems, such as security central processing units, face challenges in detecting faults injected during CRC generation, which can lead to unauthorized access and system compromise, as current methods are either too expensive or increase logic area without adequate protection.
Innovation Solution
A data processor configured to receive data units with error check data, compute a first verification value (parity) and a second verification value (CRC remainder), and compare them to verify the data unit, providing stronger protection against faults by converting weakly protected signals to strongly protected signals, thereby preventing attackers from influencing system operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strong CRC signature is added to protect data, then fault detection capability is improved, but device complexity and logic area increase
Solution Approach 1:
The patent applies preliminary action by performing a parity check on load data before the CRC generation process. This early verification step catches faults before they propagate through the expensive CRC generation logic, preventing corrupted data from being processed further and avoiding the need for additional complex protection logic throughout the system.
Solution Approach 2:
The patent segments the error detection process into two distinct stages: a first stage using simple parity checking on load data, and a second stage using CRC verification on the parity result. This segmentation allows each stage to use appropriately sized check values (1-bit parity, then 12-bit CRC), reducing the overall complexity compared to using only full-strength CRC throughout the entire data path.
2Reliability
If parity check is performed after CRC generation, then fault detection is improved, but additional logic area is required
Solution Approach 1:
The patent merges the parity check function into the existing CRC verification process by having the core compute the same parity on received data and compare it against the received parity value. This combines two verification functions into a unified process that uses existing hardware resources, avoiding the need for separate dedicated parity check logic that would increase area.
Solution Approach 2:
The core's existing verification logic is made multi-functional by using it to perform both CRC verification and parity verification. The same computational resources that verify the 12-bit CRC remainder are also used to verify the 1-bit parity, making the verification logic universal and eliminating the need for additional dedicated verification hardware.
3Reliability
If flip-flops are added to ensure parity check is not deleted, then fault detection reliability is improved, but device area increases
Solution Approach 1:
The patent applies self-service by making the core independently verify the parity of received data through computation rather than relying on external flip-flop circuits to preserve parity information. The core uses its own computational resources to recalculate and verify parity, making the system self-sufficient and eliminating the need for additional area-consuming flip-flop-based retention circuits.
Data Source
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AI summary
Described herein is a data processor (402, 501) for verifying received data, the data processor being configured to: receive (601) a data unit comprising data bits and error check data for the data unit; compute (405, 602) a first verification value over the data bits of the received data unit; compute (406, 603) a second verification value over the data bits of the received data unit and the first verification value; compare (604) the second verification value and the received error check data and verify the received data unit in dependence on that comparison. This may allow faults in the received error check data to be identified.