Fault Sensitivity Analysis for Cell-Aware ATPG Simulation Time
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Solution Overview
Problem
Current cell-aware automated test pattern generation (ATPG) methods require extensive analog simulations, leading to significant simulation times due to the need for separate runs for each cell and potential fault, which becomes prohibitive as circuit complexity increases.
Innovation Solution
The implementation of Fault Sensitivity Analysis (FSA) in analog simulators allows for the reuse of fault-free simulation results and efficient fault insertion at specific test points, enabling a single simulation run to determine detectable defects and their detection conditions, thereby reducing the overall simulation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exhaustive analog simulation is performed for each cell and potential fault to achieve complete fault coverage, then fault detection accuracy is improved, but simulation time increases significantly
Solution Approach 1:
The patent performs preliminary fault sensitivity analysis to identify which faults are actually detectable in the circuit before generating test patterns. This preliminary filtering step eliminates the need to simulate undetectable faults, significantly reducing simulation time while maintaining complete coverage of all detectable faults
Solution Approach 2:
The patent extracts and analyzes the sensitivity of individual faults to test patterns, separating detectable faults from undetectable ones. By taking out only the relevant detectable faults for further test pattern generation, the method avoids wasting simulation resources on faults that cannot be detected regardless of the test pattern applied
2Reliability
If cell-aware ATPG is implemented to detect defects inside library cells, then defect detection capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the ATPG process into distinct phases: fault extraction from cell layouts, fault sensitivity analysis, detectable fault identification, and test pattern generation. This segmentation allows each phase to be handled by specialized tools and methods, managing complexity while enabling comprehensive cell-aware defect detection
Solution Approach 2:
The patent introduces fault sensitivity analysis as an intermediary step between fault extraction and test pattern generation. This intermediary analysis acts as a filter and guide, identifying which extracted faults are actually detectable and should be targeted by test patterns, thereby simplifying the overall ATPG system architecture
3Reliability
If the number of test patterns is increased to cover more faults, then fault coverage is improved, but the time to generate and apply test patterns increases
Solution Approach 1:
The patent extracts and eliminates redundant test patterns by identifying which faults are already detected by existing patterns. By taking out only the essential test patterns needed to detect previously undetected faults, the method achieves complete fault coverage with the minimum necessary number of patterns, reducing generation and application time
Data Source
AI summary
A system, method, and computer program product for cell-aware fault model generation. Embodiments determine defects of interest for a cell, typically from cell layout and a transistor-level cell netlist. A circuit simulator performs analog fault simulation on the transistor-level netlist to determine detectable defects from the defects of interest, and detection conditions for the detectable defects. The circuit simulator employs fault sensitivity analysis (FSA) for amenable cells for greatly accelerated fault detection. Embodiments generate and output cell-aware fault models for the detectable defects from the detection conditions, for use in automated test pattern generation.