Fault-Tolerant Cache Control Device with Shadow Memory Parity
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Solution Overview
Problem
Cache memory errors due to soft errors can lead to unwanted program operations and erroneous results, as they are not effectively detected and corrected, causing faults that are visible to the processor.
Innovation Solution
A cache control device with a fault-tolerant function, comprising a cache memory and a shadow cache memory, each generating and storing parity bits using different methods, and a fault detector that performs parity checks to ensure data integrity and transmits error-free data to the processor, thereby preventing faults from being shown externally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cache memory is used to store data with higher response speed, then the access speed is improved, but the reliability deteriorates due to soft errors causing undetected faults
Solution Approach 1:
The patent creates a shadow cache memory as a copy of the main cache memory. Both caches store the same data, and the shadow cache serves as a backup for error detection and correction, resolving the reliability issue while maintaining the speed advantage of cache memory
Solution Approach 2:
The patent implements a feedback mechanism where parity bits are generated from cache data and compared with shadow cache data. When errors are detected through parity mismatch, the system feedbacks the error information to correct the faulty data, ensuring data integrity while maintaining fast access
2Reliability
If a shadow cache memory is added for error detection and correction, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent divides the cache system into two independent but synchronized segments: the main cache memory for normal operation and the shadow cache memory for error detection. This segmentation allows the system to gain reliability through redundancy while keeping each segment relatively simple in structure
3Reliability
If parity check operations are performed on both cache and shadow cache data, then the reliability is improved, but the processing time increases
Solution Approach 1:
The patent performs preliminary actions by continuously maintaining the shadow cache memory synchronized with the main cache and pre-computing parity bits. This allows error detection to occur rapidly during data access without requiring extensive processing time at the moment of access
Data Source
AI summary
The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.