Fault-Tolerant Computer With Register Arbiter And Memory Scrubber
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Solution Overview
Problem
Current computing systems used in space and high-radiation environments face significant challenges with radiation-induced failures, particularly from single event effects (SEEs), which lead to system failures despite advancements in radiation hardening techniques, resulting in performance lag and reliability issues.
Innovation Solution
A fault-tolerant computer system architecture utilizing four-modular redundancy (4MR) with custom-designed RISC-V glassbox softcore processors, an arbiter for register value correction, and a memory scrubber for data memory correction, along with partial and full reconfiguration capabilities to mitigate SEEs and ensure system resilience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If radiation hardening techniques are used, then system reliability is improved, but system performance deteriorates
Solution Approach 1:
The system is divided into multiple independent processor modules (at least two processors) that execute the same instructions independently. This segmentation allows the system to maintain high performance through parallel execution while achieving reliability through comparison of results from separate modules, avoiding the performance penalty of sequential error checking in traditional radiation-hardened systems.
Solution Approach 2:
The system implements a feedback mechanism where results from multiple processors are continuously compared by a voter circuit. When discrepancies are detected (indicating potential radiation-induced errors), the system uses feedback to identify and correct the erroneous result, maintaining both high reliability and performance by quickly resolving errors rather than preventing them proactively through slower hardening techniques.
2Reliability
If multiple processors are used for redundancy, then fault tolerance is improved, but device complexity increases
Solution Approach 1:
Multiple processor modules perform identical functions using the same instruction set architecture and operational logic. This universality simplifies the overall system design because each module is a standardized, interchangeable unit, reducing the complexity of integration and verification compared to heterogeneous redundant systems. The voter circuit also uses a simple majority-vote logic that is universally applicable regardless of the number of processor modules.
3Reliability
If real-time error detection and correction is implemented, then reliability is improved, but processing speed deteriorates
Solution Approach 1:
The system maintains continuous processing by having multiple processors operate in parallel without interruption. Error detection and correction occur continuously in the background through the voter circuit comparing results in real-time, rather than pausing execution to check for errors. This allows the system to maintain high processing speed while achieving real-time error correction, as the useful computational action continues uninterrupted across multiple parallel streams.
Data Source
AI summary
A fault-tolerant computer system includes a plurality of processors configured to simultaneously execute identical sets of processor-executable instructions, each of the plurality of processors containing a processor core including one or more registers and a local memory, an arbiter configured to read each of the registers of the plurality of processors, detect incorrect register values, and overwrite the registers containing the incorrect register values with corrected register values, and a memory scrubber configured to read each address of the local memories of the plurality of processors, detect incorrect memory values, and overwrite addresses containing the incorrect memory values with corrected memory values. In various embodiments, the computer system may be implemented using one or more field programmable gate arrays (FPGAs).