Fault Tolerant Computer Architecture With Standby CPU Failover
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Solution Overview
Problem
High reliability fault-tolerant computer systems face challenges in maintaining cost-effectiveness and processing efficiency due to the need for redundant components and periodic checkpointing, which can slow down active systems and incur significant costs for duplicate systems or slow down processing with standby systems.
Innovation Solution
A fault-tolerant computer system design with a plurality of CPU nodes, IO domains, and a Non-Transparent Bridge (NTB) PCI Express switching fabric, where one CPU node is designated as standby and the others as active, with failover mechanisms that transfer state and memory through the switching fabric to ensure seamless operation upon failure, and IO domain failover mechanisms to maintain system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two or more processor systems execute the same application simultaneously with periodic result comparison, then fault tolerance is improved, but system cost and complexity increase significantly
Solution Approach 1:
The system segments processor functionality into active and standby roles, with the standby processor maintaining identical hardware architecture but dormant execution state. This segmentation allows fault tolerance without requiring full duplication of active processing, reducing overall system complexity while maintaining the ability to compare and transfer state.
Solution Approach 2:
The standby processor performs preliminary initialization and state preparation in advance, maintaining readiness to immediately assume the active role. Checkpoint data is pre-configured and ready for rapid transfer, eliminating the need for complex real-time synchronization protocols between multiple active processors.
2Reliability
If a standby processor system receives periodic checkpoint updates from the active processor, then fault tolerance is improved, but processing speed decreases due to the overhead of checkpointing
Solution Approach 1:
The system implements periodic checkpointing where the standby processor receives updated state data at predetermined intervals rather than continuously. This periodic action minimizes the overhead impact on active processing while ensuring the standby has current state information for rapid failover.
Solution Approach 2:
A switching fabric acts as an intermediary between the active and standby processors, enabling efficient state transfer without requiring direct intervention in the active processor's execution flow. This intermediary mechanism isolates the checkpointing overhead from the critical processing path.
3Reliability
If redundant components are implemented for fault tolerance, then system reliability is improved, but cost-effectiveness deteriorates due to the expense of maintaining duplicate systems
Solution Approach 1:
The system merges the active and standby processors into a single integrated architecture sharing common resources such as memory, I/O interfaces, and cooling infrastructure. This consolidation reduces the cost of maintaining redundant components while preserving the fault tolerance benefits of having a standby processor ready to assume the active role.
Data Source
AI summary
A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.