Fault-Tolerant Computer System with Crossbar-Switch Interconnection
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Solution Overview
Problem
High-end computer systems face challenges in achieving global memory sharing and balancing transmission bandwidth and delay while maintaining system reliability due to increasing integration density and complexity in multi-path CPU systems.
Innovation Solution
A high-end fault-tolerant computer system is designed with N single junction prototype verification systems and M crossbar-switch interconnection router chipsets, where each crossbar-switch interconnection router chipset achieves internal interconnection among the N single junctions without switching between them, utilizing four-path tightly-coupled computer boards with 4 CPUs and junction controller chipsets for cache consistency and internet interface control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors is increased to meet application demands, then system capability is improved, but system reliability deteriorates due to increasing integration density
Solution Approach 1:
The system is divided into multiple independent path sets, where each path contains processors and associated resources. By segmenting the system into isolated paths, the patent reduces the propagation of failures across the entire system, thereby maintaining reliability while increasing overall system capability through parallel path operation.
Solution Approach 2:
Different paths are configured with specific local characteristics and resources, allowing each path to be optimized independently. This enables localized fault containment and repair without affecting other paths, maintaining system reliability while providing diverse computational capabilities.
2Reliability
If multi-path computer system is constructed to meet application demand, then system reliability is improved, but verification complexity increases
Solution Approach 1:
The patent uses prototype verification systems that replicate the structure and behavior of the full multi-path system. By creating simplified copies with the same verification objectives, the system reduces verification complexity while maintaining the ability to validate reliability-critical paths.
Solution Approach 2:
Verification is performed in advance using prototype systems before deploying the full multi-path configuration. This preliminary verification identifies potential issues early, reducing the complexity of verifying the complete system later while ensuring reliability requirements are met.
3Productivity
If global memory sharing is implemented in multi-path system, then resource utilization is improved, but transmission bandwidth and delay balance becomes difficult
Solution Approach 1:
The patent introduces memory management intermediaries that control and regulate memory access requests between paths. These intermediaries balance transmission loads, manage bandwidth allocation, and control access delays, enabling global memory sharing while maintaining balanced transmission characteristics.
Data Source
AI summary
The present invention provides a high-end fault-tolerant computer system and an implementation method. The system includes N single junction prototype verification systems and M crossbar-switch interconnection router chipsets. Each crossbar-switch interconnection router chipset is used to achieve the interconnection among the N single junction prototype verification systems. Switching is not performed among all crossbar-switch interconnection router chipsets, and both M and N are positive integers greater than or equal to 2. The single junction includes: a computer board, which is 4-path tightly-coupled computer board, and a junction controller for controlling 2 paths of CPUs on the computer board. The present invention can effectively realize the global memories sharing, balance the system transmission bandwidth and delay, and solve the problem of the integration reliability of multi-path CPU system.