Fault-Tolerant Floating-Point Processing for Neural Network CIM
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Solution Overview
Problem
Existing memory solutions for AI applications, such as GPUs with GDDR or HBM, are expensive and prone to reliability issues due to hardware defects and miniaturization, which affect computational accuracy and efficiency.
Innovation Solution
Implementing a fault-tolerant training (FTT) method that sets abnormal weights to a reference value during training and a fault-tolerant floating-point (FTF) format with a constrained value range to mitigate errors, ensuring stability and accuracy in neural network models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If GPU with GDDR or HBM memory is used, then memory bandwidth and capacity are improved, but cost increases
Solution Approach 1:
The patent uses standard DRAM chips that can be replaced or reconfigured, rather than expensive specialized memory. The system accepts that individual memory cells may fail but uses error correction and reconfiguration to maintain functionality, treating memory cells as disposable resources that can be substituted.
Solution Approach 2:
The patent dynamically changes operational parameters including voltage levels, refresh rates, and error correction thresholds based on detected memory cell conditions. This allows the system to adapt to aging and degradation, extending the effective lifetime of memory components while maintaining acceptable performance.
2Speed
If DRAM and logic chips are integrated with ultra-wide I/O, then memory bandwidth is improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent introduces error correction codes and parity bits as intermediary elements between the memory cells and the logic operations. These additional bits act as mediators that detect and correct errors without requiring perfect hardware reliability, enabling the use of higher-density, lower-reliability memory cells.
Solution Approach 2:
The system pre-configures redundant memory paths and error correction mechanisms before failures occur. When errors are detected, pre-established backup pathways are activated, cushioning against the impact of manufacturing defects and preventing system failure.
3Quantity of substance
If memory cells are miniaturized, then memory capacity is improved, but error rate increases
Solution Approach 1:
The patent applies different quality levels to different parts of the memory system. High-reliability error correction logic and control circuits are used in critical areas, while the bulk memory cells can operate at lower reliability thresholds. This allows miniaturization of storage elements while maintaining overall system reliability through localized quality differentiation.
4Reliability
If additional controllers are added to address reliability issues, then error correction capability is improved, but latency increases
Solution Approach 1:
The patent merges the error correction functionality directly into the memory array structure and control logic, eliminating separate controller overhead. Error detection and correction operations are performed in parallel with normal memory access operations, combining multiple functions into unified circuitry that reduces latency while maintaining reliability.
Data Source
AI summary
The application discloses a neural network system, a method, and a device for processing floating-point number. A self-defined floating-point number is obtained, wherein the self-defined floating-point number comprises a sign field, an exponent field, and a mantissa field, and a value of the self-defined floating-point number is determined by bit of the sign field, bits of the exponent field, bits of the mantissa field, and a bias value, wherein the bias value is determined by a total bit number of the exponent field. The self-defined floating-point number is applied to numerical calculations.