Fault Tolerant Microprocessor System With Parallel Core Segmentation
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Solution Overview
Problem
Current safety-critical microprocessor systems for automotive applications fail to detect and manage conceptual errors in software, leading to potential system failures and difficulties in distinguishing software defects from hardware errors, which compromises robustness and maintainability.
Innovation Solution
A microprocessor system with multiple intrinsically safe modules, each with two cores, connected via a bus system, where software modules with overlapping functions are distributed across these modules to detect and arbitrate errors, ensuring unique identification and isolation of faulty components, and enabling seamless fallback and redundancy mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n software components are executed sequentially to detect conceptual errors, then software reliability is improved, but system productivity deteriorates due to n-fold runtime requirement
Solution Approach 1:
The system divides software components into multiple independent modules that can execute in parallel on different cores. Each software component is segmented to run on separate processing units, enabling concurrent execution while maintaining error detection capabilities through the distributed architecture.
Solution Approach 2:
The patent transitions from sequential execution in a single runtime environment to parallel execution across multiple runtime environments on multiple cores. This dimensional shift from one-dimensional sequential processing to multi-dimensional parallel processing enables simultaneous error detection without n-fold runtime penalty.
2Difficulty of detecting and measuring
If hardware monitoring modules are used to detect errors, then error detection capability is improved, but the ability to distinguish software defects from hardware errors deteriorates
Solution Approach 1:
The system segments error detection across multiple independent cores, each with its own runtime environment. By distributing software components across separate processing units, the system can isolate and identify whether errors originate from hardware or software by observing which specific core or module fails, preserving error source information.
Solution Approach 2:
The patent introduces a communication bus system as an intermediary between multiple cores. This bus enables the system to monitor and distinguish error sources by observing communication patterns and error signals from individual cores, allowing differentiation between hardware failures and software defects while maintaining overall error detection capability.
3Reliability
If software modules are distributed across multiple microprocessor modules, then system robustness is improved, but device complexity increases
Solution Approach 1:
The system segments software functionality into distributed modules across multiple microprocessor cores, with each core handling specific software components. This segmentation provides robustness through distribution while managing complexity by organizing modules in a structured, modular fashion that can be independently developed and maintained.
Solution Approach 2:
The patent employs multiple cores that can execute different software modules, making each core a universal processing unit. This multi-functionality allows the same hardware architecture to handle diverse software tasks while maintaining a relatively simple underlying device structure, as the cores can be dynamically assigned to different functions based on system needs.
Data Source
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AI summary
The invention relates to a microprocessor system (MCUSA) for executing software modules, at least some of which are security-critical, within the scope of controlling functions or tasks assigned to the software modules, comprising an intrinsically safe microprocessor module (HWSAi) having at least two microprocessor cores (CPUi). According to the invention, at least one further intrinsically safe microprocessor module (HWSAi i=1,... n) having at least two microprocessor cores (CPU1, CPU2; CPU3, CPU4) is provided, wherein the at least two microprocessor modules (HWSA1, HWSA2) are connected via a bus system (B), at least two software modules are provided which execute functions, at least some of which overlap, said software modules having at least partially overlapping functions are distributed on a microprocessor module (HWSA1, HWSA2) or on at least two microprocessor modules (HWSA1, HWSA2), and means for comparing and/or arbitrating events generated with the software modules for the identical functions are provided in order to detect software and/or hardware faults.