Fault Tolerant Page Stripes in Low Density Memory
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Solution Overview
Problem
Low density memory systems face data loss and reconstruction challenges due to proximity of data pages on adjacent wordlines, leading to overprovisioning penalties when implementing fault tolerant redundancy schemes.
Innovation Solution
Implementing fault tolerant page stripes with dynamically adjusted sizes, where each stripe includes multiple data pages from every plane with sufficient wordline separation, and the last page dedicated to redundancy metadata for error detection and correction, using a memory sub-system controller to manage data storage and compute XOR metadata efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault tolerant redundancy schemes are implemented in low density memory systems, then data reliability is improved, but memory capacity is reduced due to overprovisioning penalties
Solution Approach 1:
The memory device is divided into multiple planes, with each plane containing multiple logical units and blocks. Data pages are distributed across different planes rather than being concentrated in one location, enabling fault tolerance while optimizing capacity utilization in low density memory systems
Solution Approach 2:
The patent organizes data storage across multiple dimensional hierarchies: planes → logical units → blocks → data pages. This multi-dimensional organization allows the system to achieve fault tolerance by distributing data across planes (adding a spatial dimension) without requiring excessive redundant capacity
2Quantity of substance
If data pages are stored on adjacent wordlines to maximize memory utilization, then memory capacity is improved, but the likelihood of simultaneous failures increases
Solution Approach 1:
Data pages within the same logical unit are segmented across different planes. Each plane contains multiple blocks with data pages separated by wordlines, ensuring that pages are physically separated in the memory structure. This segmentation maintains high memory utilization while preventing simultaneous failures of all pages in a logical unit
Solution Approach 2:
The patent applies different storage strategies to different parts of the memory hierarchy. At the plane level, data is distributed across multiple planes; at the block level, data pages are arranged with wordline separation. This localized quality approach optimizes both utilization and reliability at different levels of the memory structure
Data Source
AI summary
An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.