Fault Tolerant Switch With Parallel Clamp Circuit

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Solution Overview

Problem

Electronic circuits are vulnerable to transient overstress events such as electrostatic discharge (ESD) and electrical overstress (EOS), which can cause damage due to overvoltage conditions and high power dissipation, leading to issues like junction damage and surface charge accumulation.

Innovation Solution

A fault-tolerant switch is designed with a p-type and n-type field effect transistor (PFET and NFET) in series, coupled with a clamp circuit that includes diodes and FETs in parallel for overvoltage protection, and a gate driver for controlling the switch, providing robust protection against ESD and EOS events while maintaining low leakage and accurate signal processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a clamp circuit with diodes and FETs is added for overvoltage protection, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveprotection against overstress eventsVSAvoidcircuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The clamp circuit is integrated directly into the switch device, merging the protection function with the switching function. The clamp shares the same substrate and physical space as the switch transistors, eliminating the need for separate external protection components and reducing overall system complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The clamp circuit is designed to handle multiple types of overstress events including ESD and EOS through a unified structure. The same clamp transistors and diodes provide protection across different stress conditions, making the protection mechanism versatile and reducing the need for multiple specialized protection circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If the clamp circuit is designed to activate during overstress, then protection capability is improved, but power dissipation increases

Engineering Contradiction:

Improveovervoltage protectionVSAvoidpower dissipation

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The clamp circuit uses dynamically controlled FETs that adjust their conductivity based on the stress conditions. During normal operation, the clamp FETs remain off to minimize leakage and power dissipation. During overstress events, the FETs activate to provide protection, creating a dynamic response that balances protection capability with energy efficiency.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The gate bias circuits modify the electrical parameters of the clamp FETs based on detected stress conditions. By changing the gate voltage parameters, the clamp transitions from a high-impedance low-power state to a low-impedance high-protection state, allowing the circuit to optimize between power dissipation and protection capability depending on operational conditions.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If the switch uses series PFET and NFET configuration, then on-state impedance control is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveon-state impedance controlVSAvoidfabrication complexity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The gate bias circuits automatically adjust the gate voltages of the series PFET and NFET to maintain precise on-state impedance control without requiring external calibration or manual adjustment. The bias circuits self-regulate based on the transistor characteristics, compensating for manufacturing variations and ensuring consistent impedance control across production batches.

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution ensures reliable operation with low power dissipation and high reliability in the presence of overstress events, protecting the switch from damage and maintaining accurate signal processing by controlling on-state and off-state impedance.

Implementation Method 1

a forward protection circuit including a first diode and a first clamp FET in series between the first pad and the second pad

Methodology Applied

Scientific EffectDiode forward conduction: Diode

Implementation Method 2

a switch including a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series

Methodology Applied

Scientific EffectField effect transistor conduction control:

Data Source

PatentUS10581423B1Fault tolerant low leakage switch

Publication Date: 2020.03.03 ANALOG DEVICES GLOBAL UNLTD

AI summary

Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.