Fault Tree Analysis Weeding k/n Conjunctions
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Solution Overview
Problem
Traditional fault tree analysis methods face memory overflow issues due to factorial space complexity when evaluating large and complex k/n gates, leading to failure in systems like server clusters of data centers, as they do not accurately evaluate the orders of k/n gates and expand them repeatedly, resulting in a huge number of overlong conjunctions.
Innovation Solution
A fault tree analysis system that includes k/n conjunction weeding means to evaluate the orders of disjoint basic and simple k/n gates without expansion, removing conjunctions exceeding a given maximal order, thereby weeding out overlong conjunctions early in the evaluation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional expanding algorithms are used to evaluate k/n gates, then complete evaluation of minimal cut sets is achieved, but memory usage increases factorially leading to overflow
Solution Approach 1:
The patent extracts and removes overlong conjunctions from the evaluation process using a weeding algorithm. By identifying and eliminating conjunctions that exceed the maximal order M, the system prevents factorial memory growth while maintaining evaluation completeness for valid minimal cut sets.
Solution Approach 2:
The patent applies preliminary ordering evaluation to conjunctions before full expansion. By calculating the order of each conjunction and comparing it against the maximal order M in advance, the system performs pruning early in the evaluation process, preventing unnecessary expansion of overlong conjunctions that would consume excessive memory.
2Measurement precision
If k/n gates are expanded repeatedly until k=1 or k=n, then accurate evaluation is achieved, but computation time increases due to factorial space complexity
Solution Approach 1:
The patent performs preliminary order evaluation of conjunctions containing k/n gates before full expansion. By calculating the order metric and comparing against maximal order M in advance, the system identifies overlong conjunctions that would require excessive computation time, pruning them before expensive expansion operations occur.
Solution Approach 2:
The patent extracts and removes overlong conjunctions from the evaluation pipeline using the weeding algorithm. This eliminates the need to perform repeated expansions on conjunctions that would exceed the maximal order, significantly reducing computation time while preserving accurate evaluation of valid minimal cut sets.
3Ease of manufacture
If traditional weeding algorithms treat k/n gate orders as zero, then algorithm simplicity is maintained, but overlong conjunctions cannot be identified and removed
Solution Approach 1:
The patent changes the parameter used to represent k/n gate contribution from zero (traditional approach) to the actual order metric (improved approach). By evaluating the real order of k/n gates based on their inputs and the maximal order M, the system maintains the simplicity of the weeding algorithm while significantly improving its ability to identify and remove overlong conjunctions.
Data Source
AI summary
The present invention is a fault tree analysis system, comprising: k/n conjunction weeding means for weeding a conjunction including disjoint basic k/n gates and/or disjoint simple k/n gates and removing the conjunction if its order is greater than a given maximal order of minimal cut sets.