Component Fault Tree Verification Using Fault Effect Simulation
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Solution Overview
Problem
The evaluation of component fault trees in safety-critical systems, such as those in aviation and medical technology, is costly and time-consuming, particularly due to the increasing complexity of embedded systems, necessitating a more efficient method for assessing system security and quality.
Innovation Solution
A computer-aided method for checking component fault trees involves executing a fault effect simulation, stimulating error states with specified disturbances, detecting stimulation errors, and verifying the component fault tree by comparing these errors with predefined error states, allowing for a quick and comprehensive assessment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional safety analysis methods (FMEA, FTA) are used to evaluate component fault trees, then system security and quality are assessed, but development costs and development time increase significantly
Solution Approach 1:
The patent creates a virtual model (copy) of the technical system that replicates the fault tree structure and component relationships. This virtual model allows safety analysis to be performed on the copy rather than the actual system, significantly reducing development time and costs while maintaining assessment accuracy for system security and quality
Solution Approach 2:
The patent replaces traditional manual safety analysis methods (FMEA, FTA) with an automated computer-based simulation system. The simulation automatically evaluates the component fault tree by injecting error signals and tracking fault propagation, eliminating the need for time-consuming manual analysis while improving efficiency and reducing development time
2Reliability
If traditional safety analysis methods are used to evaluate component fault trees, then system security is assessed, but development costs increase
Solution Approach 1:
By creating and analyzing a virtual model of the system rather than performing extensive manual safety analyses on the actual system, the patent reduces development costs. The virtual model allows repeated testing and evaluation without additional physical resources or expert manual intervention
Solution Approach 2:
The simulation system automatically performs safety analysis by injecting error signals, tracking fault propagation through the component fault tree, and generating evaluation results without requiring extensive manual intervention. This automation reduces the need for expensive expert analysis while maintaining thorough safety assessment
3Measurement precision
If error states are stimulated with specified disturbances in the simulation, then stimulation errors are detected and component fault tree correctness is verified, but the checking process becomes more complex
Solution Approach 1:
The patent segments the safety checking process into distinct automated steps: injecting error signals at specific input locations, tracking fault propagation through defined paths in the component fault tree, detecting stimulation errors at output locations, and comparing results against expected outcomes. This structured segmentation improves checking precision while the automation manages the apparent complexity
Data Source
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AI summary
The invention relates to a method for computer-aided verification of a component fault tree for a technical system, in which a processor performs the following process steps. The method comprises a first process step for performing a fault effect simulation for the technical system using the component fault tree, wherein the component fault tree comprises fault states for components of the technical system that are generated by predefined disturbances to the components. The predefined disturbances are assigned to the fault states. The method further comprises a second process step for stimulating the fault effect simulation with the predefined disturbances, wherein the predefined disturbances are transmitted to the components as fault signals. The method further comprises a third process step for detecting stimulation errors that are generated by stimulating the fault effect simulation.Additionally, the procedure includes a fourth step for verifying the component fault tree by comparing the stimulation errors with the fault states, providing an initial control signal that indicates the correctness of the component fault tree if the stimulation errors substantially match the fault states.