Single-Line Fault Voltage Encoding for Power Domain Detection
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Solution Overview
Problem
The increasing demand for early fault detection in silicon circuits, particularly in systems using Fast Voltage Mode (FVM) and zero load-line techniques, is hindered by traditional solutions that require additional pins, leading to cost and footprint issues, while existing pin-efficient methods introduce latency and protocol complexity.
Innovation Solution
A system that encodes multiple fault conditions using unique analog voltage levels on a single output line, generated by a current sink circuit, allowing the SoC to identify specific fault categories without additional pins, thus reducing latency and maintaining compatibility with legacy systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dedicated pins are used for fault signaling, then fault detection capability is improved, but pin count and device complexity increase
Solution Approach 1:
The patent combines multiple fault condition signals into a single output line by encoding different fault types as distinct voltage levels. The voltage regulator controller monitors multiple power domains and system conditions, then encodes the detected fault condition as a specific voltage level on a single output line, eliminating the need for multiple separate fault pins while maintaining comprehensive fault detection capability.
Solution Approach 2:
The patent changes the parameter being transmitted on the output line from binary (present/absent) to multi-level voltage encoding. Different voltage levels represent different fault conditions, allowing a single line to convey multiple distinct fault types. This parameter transformation enables the system to maintain high reliability for fault detection while reducing pin count.
2Loss of information
If polling registers via SVID or system management bus is used to identify fault root cause, then fault identification capability is improved, but latency and software burden increase
Solution Approach 1:
The patent performs preliminary encoding of the fault root cause at the voltage regulator controller before transmission to the SoC. The controller identifies which power domain or system condition caused the fault and encodes this information into the voltage level on the output line. This preliminary action eliminates the need for the SoC to poll registers or execute software routines to identify the fault source, thereby reducing latency and software burden while maintaining complete fault identification capability.
3Adaptability or versatility
If traditional binary fault signaling is used, then system compatibility is improved, but fault specificity and performance optimization are reduced
Solution Approach 1:
The patent extends traditional binary fault signaling by introducing multi-level voltage encoding while maintaining compatibility with legacy systems. The output line can operate in either binary mode for legacy compatibility or multi-level mode for enhanced fault specificity. Different voltage levels provide detailed fault information including specific power domain failures and system conditions, enabling performance optimization through selective IP throttling or frequency demotion based on the identified fault source.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables immediate, targeted responses to specific fault conditions, reducing unnecessary throttling and optimizing performance by identifying and addressing the root cause of faults within the SoC, while preserving backward compatibility and reducing pin count.
Implementation Method 1
a current sink circuit configured to generate, for each distinct fault condition, a corresponding current level that produces a corresponding voltage level on the output line
Data Source
AI summary
A voltage regulator controller, including: detection circuitry configured to detect a plurality of distinct fault conditions associated with one or more power domains or system-level operating conditions, wherein the distinct fault conditions include different categories of faults or a same category of fault occurring in different power domains; and a current control circuit coupled to a single output line, the current control circuit configured to, for each detected fault condition, generate a corresponding current level that produces a corresponding voltage level on the output line, wherein each voltage level corresponds to a different fault condition.