FB-DIMM to DDR Translator Parallel Write Channels
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Solution Overview
Problem
Current FB-DIMM technology is limited by the single DDR bus per Advanced Memory Buffer (AMB), restricting simultaneous write operations and increasing latency, while also being costly and power-hungry due to the need for multiple AMBs, which limits bus bandwidth and increases system costs and cooling requirements.
Innovation Solution
The introduction of a FB-DIMM to DDR translator that allows for multiple DDR buses, enabling simultaneous write operations and reducing the number of AMBs required, thereby increasing bandwidth and capacity while maintaining compatibility with existing memory host controllers and supporting both serial and parallel memory technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single AMB is used per channel in FB-DIMM technology, then device complexity is reduced, but write performance and bandwidth are limited due to sequential write operations
Solution Approach 1:
The patent divides the single AMB function into multiple independent write channels. Each write channel can independently receive and process write commands, allowing parallel write operations. This segmentation enables multiple simultaneous write transactions without requiring multiple full AMBs, thus improving write performance while controlling complexity.
Solution Approach 2:
The patent introduces a new dimension by separating write operations from read operations and enabling independent write channels. Instead of sequential write operations through a single AMB, the system creates multiple parallel write paths that operate simultaneously, transforming the write operation from a single-dimensional sequential process to a multi-dimensional parallel process.
2Productivity
If multiple AMBs are used to increase bandwidth, then write performance improves, but system cost and power consumption increase
Solution Approach 1:
The patent segments the AMB functionality into multiple simplified write channels rather than using multiple complete AMBs. Each write channel is a lightweight independent unit that can operate simultaneously, achieving high bandwidth without the full power consumption and cost of multiple complete AMBs.
Solution Approach 2:
The patent applies partial action by implementing only the necessary write channel functionality without requiring complete AMBs for each channel. This partial implementation achieves sufficient bandwidth performance while significantly reducing power consumption and system cost compared to using multiple full AMBs.
3Quantity of substance
If multiple AMBs are deployed to support more ranks, then capacity increases, but cooling requirements and system cost increase
Solution Approach 1:
The patent segments the memory subsystem into multiple independent write channels that can service different ranks simultaneously. This segmentation allows the system to support more ranks (increasing capacity) without proportionally increasing the number of AMBs, thereby controlling thermal generation and cooling requirements.
Solution Approach 2:
The patent enables simultaneous operations across multiple dimensions by creating independent write channels that can process commands for different ranks in parallel. This dimensional expansion allows increased capacity through additional ranks without a corresponding increase in thermal load, as operations are distributed across multiple independent channels rather than concentrated in fewer AMBs.
Data Source
AI summary
A translator of an apparatus in an example employs a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) to write to a plurality of parallel protocol memory module channels that comprises a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).