FBB-Biased Ring Oscillator TRNG for Higher Thermal Noise Entropy
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Solution Overview
Problem
Current True Random Number Generators (TRNGs) face challenges in meeting the increasing demands of cryptography, particularly in lightweight cryptography for IoT and the emergence of quantum computing, due to limitations in entropy generation and noise sources, which affect the unpredictability and security of cryptographic primitives.
Innovation Solution
A TRNG design utilizing Fully Depleted Silicon-On-Insulator (FD-SOI) transistors with Low Voltage Threshold (LVT) and Forward Body Biasing (FBB) to reduce scintillation noise, enhancing the calculation of thermal noise entropy, and a circuit to detect the maximum thermal noise contribution, optimizing the number of oscillations for improved entropy quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ring oscillators are used in parallel to meet entropy standards, then the entropy generation quality improves, but the power consumption and device complexity increase
Solution Approach 1:
The patent changes the electrical parameters of the transistor by applying forward body bias (FBB) to reduce the threshold voltage. This parameter modification allows the ring oscillator to operate with optimized noise characteristics, achieving high entropy quality with a single oscillator instead of requiring multiple parallel oscillators, thereby reducing power consumption and device complexity
Solution Approach 2:
The patent dynamically adjusts the body bias voltage to optimize the transistor operation point. By dynamically controlling the threshold voltage through FBB, the system can maximize thermal noise contribution while minimizing scintillation noise, achieving optimal entropy generation quality with reduced hardware requirements
2Productivity
If the threshold voltage of transistors is lowered to increase oscillation frequency, then the productivity improves, but the scintillation noise increases reducing entropy quality
Solution Approach 1:
The patent applies forward body bias to dynamically adjust the threshold voltage parameter. This allows the system to operate at optimal points where the threshold voltage is low enough to maintain high oscillation frequency but not so low that scintillation noise dominates, thus simultaneously achieving high productivity and high entropy quality
Solution Approach 2:
The patent uses periodic switching between different body bias conditions to optimize the noise characteristics. By periodically adjusting the bias state, the system can maximize thermal noise contribution during specific phases while minimizing scintillation noise, achieving high entropy quality at high oscillation frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the quality of entropy generation, enhancing the security and reliability of TRNGs by maximizing thermal noise contribution while minimizing scintillation and quantization noise, thus addressing the constraints of modern cryptographic requirements.
Implementation Method 1
Thermal noise is perfectly white, i.e. uncorrelated, and therefore contributes to the generation of a perfectly unpredictable random element
Implementation Method 2
scintillation noise (or 'flicker' noise). Thermal noise is perfectly white, i.e. uncorrelated, and therefore contributes to the generation of a perfectly unpredictable random element. Conversely, scintillation noise is an auto-correlated noise that induces predictability in the jitter
Implementation Method 3
the source of randomness of the TRNG is the jitter of the RO(s), i.e. the difference between the theoretical period and the actual period of the output signal of the or each RO
Data Source
Figure 1~3
Figure 4~5
AI summary
Random number generator comprising at least one ring oscillator (104) comprising at least one inverter (112.1 - 112.n) formed by at least two FDSOI LVT transistors (116.1, 117.1), one being of type NMOS and the other being of type PMOS, characterized in that it further comprises a circuit (128) for applying voltages to the back gates of the transistors (116.1, 117.1) configured to bias the transistors (116.1, 117.1) in FBB mode.