Floating Body Cell Memory Refresh Control
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Solution Overview
Problem
The integration degree of semiconductor memory apparatuses is limited due to the conventional structure of dynamic random access memory (DRAM) cells, which are not suitable for reducing the area of the memory core region, and the floating body cell (FBC) technology has not been effectively utilized due to the lack of developed circuits for voltage supply to memory cell transistors.
Innovation Solution
A semiconductor memory apparatus and refresh control method that includes a memory cell block with FBC transistors, a refresh controller, row and column operation controllers, and data bus switches to manage voltages and signals for read, write, and refresh operations, enabling the implementation of FBC technology by sharing source lines and sequentially activating word and source lines for efficient data rewriting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional DRAM cell structure is used, then data storage function is maintained, but memory core region area cannot be reduced
Solution Approach 1:
The patent merges the transistor and capacitor functions into a single FBC transistor structure. The floating body region acts as both the transistor channel and the charge storage element, eliminating the need for separate capacitor structures and reducing memory core area while maintaining data storage capability
Solution Approach 2:
The FBC transistor serves multiple functions: it acts as a switching transistor for data access and simultaneously functions as a memory cell for data storage through its floating body charge accumulation capability. This multi-functionality reduces the number of components needed in the memory structure
2Adaptability or versatility
If FBC technology is implemented, then integration degree is improved, but circuit complexity increases due to voltage supply requirements
Solution Approach 1:
The same voltage supply circuit is used for both normal data operations and refresh operations. The circuit generates appropriate voltage levels (VBL, VSL, VWL) that serve multiple purposes: enabling read/write operations and performing refresh operations, thereby reducing overall circuit complexity
Solution Approach 2:
The voltage supply circuit dynamically adjusts voltage levels based on operation mode. During refresh operations, the circuit provides specific voltage sequences to the FBC transistor to enable charge accumulation and maintenance, while during normal operations it provides different voltage levels for read/write functions
3Area of moving object
If FBC transistors are used, then memory cell area is reduced, but refresh operation complexity increases
Solution Approach 1:
The refresh operation uses periodic voltage pulses applied to the gate and source of the FBC transistor. By applying voltages at specific intervals and sequences, the floating body charge is periodically reinforced to maintain data without requiring complex continuous control mechanisms
Solution Approach 2:
The FBC transistor structure inherently maintains charge in the floating body region through its physical structure. The refresh operation simply needs to provide periodic voltage reinforcement rather than complex active control, allowing the structure to largely maintain itself
Data Source
AI summary
A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal.