FBMC Receiver Architecture Reducing Complexity
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Solution Overview
Problem
Current FBMC receiver implementations face complexity and inflexibility due to the need for specific processing chains for different prototype filter sizes and oversampling factors, which hinders their adoption in flexible 5G communication systems, especially when using short prototype filters that increase latency and reduce robustness to multipath reflections.
Innovation Solution
A novel FBMC receiver architecture that combines frequency domain equalization and demodulation, utilizing a frequency domain transposition unit, an equalizer, circular convolution units, and adders to process blocks of samples, allowing for adaptable implementation with short prototype filters and various FBMC schemes, thereby reducing implementation complexity and supporting multiple prototype filters and oversampling factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If specific processing chains are implemented for different prototype filter sizes and oversampling factors, then FBMC receiver can handle various transmission parameters, but device complexity increases
Solution Approach 1:
The patent implements a universal FBMC receiver architecture that can process multiple prototype filter sizes and oversampling factors through a single processing chain. The system uses configurable buffer sizes and flexible memory access patterns to accommodate different transmission parameters without requiring separate dedicated processing chains for each configuration, thereby achieving multi-functionality while controlling complexity.
2Loss of time
If short prototype filters are used to reduce latency, then throughput increases, but robustness to multipath reflections decreases
Solution Approach 1:
The patent combines frequency domain equalization with time domain filtering in a unified processing architecture. The frequency domain equalizer compensates for channel effects including multipath reflections, while the time domain prototype filter provides spectral shaping. This merging of processing domains allows the system to use short prototype filters for low latency while the frequency domain equalization maintains robustness against multipath reflections.
3Productivity
If overlapping of successive FBMC symbols is performed, then throughput is maintained despite oversampling, but inter-symbol and inter-carrier interference increases
Solution Approach 1:
The patent implements frequency domain equalization that acts as a feedback mechanism to cancel inter-symbol and inter-carrier interference generated by the overlapping process. The equalizer uses knowledge of the channel and overlapping structure to compute correction coefficients that eliminate the harmful interference, allowing the system to maintain high throughput through symbol overlapping while compensating for the resulting interference.
Data Source
AI summary
An FBMC equalization and demodulation unit and corresponding method to process an FBMC signal includes FBMC symbols, each FBMC symbol comprising data mapped over M subcarriers, oversampled by a factor K, filtered by a prototype filter and transposed in the time-domain, comprising: a frequency domain transposition unit, configured to transpose a block of P*KM samples comprising at least one FBMC symbol into frequency domain samples, where P is an integer greater than one, an equalizer unit configured to multiply the frequency domain samples by one or more coefficients computed from a propagation channel estimate, at least one circular convolution unit, configured to perform P circular convolutions between subsets of the equalized samples and a frequency domain response of a frequency shifted version of the prototype filter, and adders, to sum corresponding outputs of each of the P circular convolutions.