FC HDD Control Circuit Optimization via Hierarchical Address Decoding
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Solution Overview
Problem
The increasing number of hard disk drives (HDDs) in a Fiber Channel (FC) loop system requires a large number of complex programmable logic devices (CPLDs) for address selection signals, leading to increased costs and space constraints on the mid-plane, as conventional designs struggle to accommodate the growing demand.
Innovation Solution
A method optimizing control circuits for FC HDDs by determining subsystems and HDDs, analyzing binary values, enumerating logic combinations, selecting required logic components, and calculating shared output pins to reduce the number of logic components and simplify hardware design, allowing up to 24 HDDs to share control signals, thereby decreasing mid-plane space and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of HDDs in a FC loop system is increased to meet technology development requirements, then the system capacity and storage capability are improved, but the number of CPLD chips or CPLD pins required for address selection signals increases, resulting in increased cost and space requirements on the mid-plane
Solution Approach 1:
The patent merges the functionality of multiple CPLD chips into a single CPLD chip by implementing a hierarchical address selection architecture. The mid-plane uses a first CPLD chip to generate intermediate address signals, which are then used by second CPLD chips at the HDD connector level to generate final address selection signals. This consolidation reduces the total number of CPLD chips and pins required on the mid-plane while supporting an increased number of HDDs.
Solution Approach 2:
The patent segments the address selection signal generation into two levels: a first level on the mid-plane using a CPLD chip to generate intermediate address signals based on system address signals, and a second level at HDD connectors using additional CPLD chips to generate final address selection signals. This segmentation allows the system to support more HDDs without proportionally increasing mid-plane complexity, as the second level operates independently with shared intermediate signals.
2Adaptability or versatility
If more CPLD chips are placed on the mid-plane to provide sufficient control signals for more HDDs, then the address selection capability is improved, but the available space on the mid-plane decreases due to more HDD connectors and thermal holes
Solution Approach 1:
The patent merges address selection functionality from distributed CPLD chips into a centralized first CPLD chip on the mid-plane, which generates intermediate address signals. This consolidation reduces the total footprint of logic devices on the mid-plane while maintaining the ability to address a large number of HDDs through efficient signal sharing and hierarchical decoding.
Solution Approach 2:
The patent moves part of the address selection functionality from the two-dimensional mid-plane to the three-dimensional system architecture by placing second CPLD chips at the HDD connector level. This dimensional redistribution allows intermediate address signals to be generated once on the mid-plane and then distributed to multiple connectors, reducing mid-plane space requirements while maintaining full address selection capability.
3Quantity of substance
If conventional CPLD design is used to provide control signals for each address selection signal, then the system can support the required number of HDDs, but the hardware design complexity and CPLD programming workload increase
Solution Approach 1:
The patent segments the complex address selection logic into two simpler stages: the first CPLD chip on the mid-plane handles high-order address decoding to generate intermediate signals, while the second CPLD chips at connectors handle low-order address decoding using these intermediate signals. This segmentation reduces the logic complexity within each CPLD device and simplifies programming, as each device only needs to handle a portion of the address decoding rather than the entire address space.
Solution Approach 2:
The patent introduces intermediate address signals as a mediator between the system address signals and the final address selection signals. The first CPLD chip generates these intermediate signals that serve as inputs for the second CPLD chips, breaking down the complex direct mapping from system addresses to HDD connectors into manageable stages with reduced programming complexity at each level.
Data Source
AI summary
A method for optimizing control circuit for FC HDDs in a system includes determining the number of subsystems supported in a FC loop and the number of HDDs to be supported in each of the subsystems, analyzing binary values of address of all HDDs for each of the subsystems, enumerating logical variations of the address selection signals according to the analyzed binary values to obtain logic combinations for the address selection signals, analyzing logic relations between these logic combinations and a system address signal, selecting logic components required according to the found logic relations, and calculating the total number of required logic components and the number of address selections signals that can share an output pin of each of the required logic components based on properties of output pins of the logic components and maximum input current of the address selection signals.