FCN Iris Recognition on FPGA via Quantization
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Solution Overview
Problem
Existing iris recognition systems face challenges in achieving efficient and accurate processing due to computationally intensive fully convolutional network (FCN) architectures, which are not optimized for resource-constrained embedded systems, leading to high computational complexity and limited deployment on mobile and wearable devices.
Innovation Solution
A three-step software/hardware co-design methodology is employed, including FCN architectural exploration, precision quantization using 8-bit dynamic fixed-point format, and hardware acceleration, to develop a resource-efficient iris recognition pipeline with FCN-based segmentation, contour fitting, and Daugman normalization and encoding, implemented on an embedded FPGA platform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If FCN-based segmentation is used for accurate iris recognition, then segmentation accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies precision quantization by changing the data representation parameter from high-precision floating-point to 8-bit dynamic fixed-point format. This parameter change reduces the computational complexity and resource requirements while maintaining segmentation accuracy, directly resolving the contradiction between accuracy and complexity.
Solution Approach 2:
The patent substitutes the software-based FCN implementation with a dedicated hardware accelerator circuit. This replacement transforms the computational mechanism from software processing to hardware processing, significantly reducing computational complexity and enabling deployment on resource-constrained embedded systems while preserving segmentation accuracy.
2Measurement precision
If FCN-based segmentation is used for accurate iris recognition, then segmentation accuracy is improved, but processing time increases
Solution Approach 1:
The patent replaces the software-based FCN processing with a hardware accelerator, fundamentally changing the processing mechanism from sequential software execution to parallel hardware computation. This substitution dramatically reduces processing time while maintaining segmentation accuracy, resolving the contradiction between accuracy and processing speed.
Solution Approach 2:
The patent performs precision quantization to 8-bit dynamic fixed-point format before hardware implementation. This preliminary action prepares the data in a format optimized for hardware processing, enabling faster computation while preserving the accuracy needed for segmentation, thus reducing processing time without sacrificing accuracy.
3Measurement precision
If full-precision floating-point FCN is implemented, then segmentation accuracy is improved, but resource utilization increases
Solution Approach 1:
The patent changes the precision parameter from full-precision floating-point to 8-bit dynamic fixed-point format. This parameter change reduces the quantity of computational resources (registers, memory, arithmetic units) required while maintaining segmentation accuracy, directly resolving the contradiction between accuracy and resource utilization.
Solution Approach 2:
The patent uses lower-precision 8-bit fixed-point arithmetic instead of high-precision floating-point arithmetic. This substitution uses a simpler, less resource-intensive computational representation that consumes fewer hardware resources while maintaining sufficient accuracy for iris segmentation, resolving the resource utilization contradiction.
Data Source
AI summary
A method of accelerated iris recognition includes acquiring an image comprising at least an iris and a pupil, segmenting the iris and the pupil using a fully convolutional network (FCN) model, normalizing the segmented iris, encoding the normalized iris, the normalizing and encoding using a rubber sheet model and 1-D log Gabor filter, and masking the encoded iris.