FCVD Dielectric Annealing for Low-Impurity STI Isolation
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in achieving high integration density while maintaining the quality of dielectric layers, particularly in terms of impurity levels, density, and etch resistance.
Innovation Solution
A multi-step anneal process is employed, involving a first anneal step using wet steam at a low temperature for a long time, an intermediate anneal step using wet steam at a higher temperature, and a final dry anneal step at an even higher temperature, to improve the quality of flowable chemical vapor deposition (FCVD) conversion and reduce nitrogen impurity levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single-step high-temperature anneal process is used to improve dielectric layer quality, then conversion ratio and density improve, but nitrogen impurity levels increase and thermal budget increases risking damage to device features
Solution Approach 1:
The anneal process is divided into multiple sequential steps with different temperature profiles and atmospheric conditions. The first anneal step uses a lower temperature with nitrogen-containing atmosphere to promote conversion and density, while the second anneal step uses a higher temperature with oxygen-containing atmosphere to remove nitrogen impurities. This segmentation allows each step to optimize for its specific function without the harmful side effects of a single high-temperature step.
Solution Approach 2:
The patent changes multiple parameters throughout the anneal process including temperature, atmospheric composition (nitrogen-containing vs. oxygen-containing), and duration. By dynamically adjusting these parameters in sequence, the process achieves high conversion ratio and density in the first step, then removes nitrogen impurities in the second step, ultimately achieving high dielectric layer quality without excessive nitrogen contamination.
2Manufacturing precision
If a single-step high-temperature anneal process is used to improve dielectric layer density, then conversion ratio improves, but thermal budget increases risking damage to semiconductor device features
Solution Approach 1:
The anneal process is segmented into two distinct steps with different temperature profiles. The first anneal step operates at a lower temperature (e.g., 400-600°C) to achieve the majority of conversion and density improvement, while the second anneal step operates at a higher temperature (e.g., 600-800°C) for a shorter duration to remove nitrogen impurities. This segmentation reduces the cumulative thermal exposure compared to a single high-temperature step while achieving superior overall quality.
Solution Approach 2:
The first anneal step performs the preliminary action of converting the flowable dielectric material and establishing high density at a lower temperature. This preliminary conversion creates a more stable structure that requires less extreme thermal processing in the subsequent step, thereby reducing the overall thermal budget needed to achieve the final high-quality dielectric layer.
3Productivity
If minimum feature sizes are reduced to achieve high integration density, then more components can be integrated into a given area, but maintaining dielectric layer quality becomes more difficult
Solution Approach 1:
The patent employs precise control and sequential changes of multiple process parameters including temperature, atmospheric composition, and anneal duration. The first anneal step uses nitrogen-containing atmosphere at lower temperature to promote conversion, followed by the second anneal step using oxygen-containing atmosphere at higher temperature to remove nitrogen impurities. This precise parameter control ensures high dielectric layer quality even in scaled-down features where impurity effects are more pronounced.
Solution Approach 2:
The two-step anneal process provides continuous improvement of dielectric layer quality through sequential actions. The first step continuously converts the flowable material and builds density, while the second step continuously removes nitrogen impurities. This continuous useful action ensures that even as feature sizes are reduced, the dielectric layers maintain high quality standards necessary for reliable device operation at high integration densities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-step anneal process achieves a high ratio of FCVD conversion with low nitrogen impurity, enhancing the quality of dielectric layers and reducing the thermal budget, thereby minimizing the risk of damaging semiconductor device features.
Implementation Method 1
a first anneal step that heats a flowable dielectric film using a wet steam at a low temperature for a relatively long time
Implementation Method 2
The multi-step anneal process can achieve high ratio of FCVD conversion and low nitrogen impurity
Implementation Method 3
a first anneal step that heats a flowable dielectric film using a wet steam at a low temperature
Implementation Method 4
Flowable chemical vapor deposition (FCVD) using multi-step anneal treatment
Data Source
AI summary
FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.


