Hierarchical ECC Decoders for Memory Latency-Reliability Tradeoffs
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Solution Overview
Problem
Current error correction codes (ECCs) in memory systems face challenges in balancing low latency with high correction capability, particularly in emerging memory technologies like phase-change memory, magnetoresistive random access memory, and 3D XPoint memory, where storage applications can tolerate variable access latencies.
Innovation Solution
The implementation of a hierarchical decoding scheme using fast decoding (FD) and accurate decoding (AD) decoders, where FD decoders flag errors with high probability and low latency, and AD decoders correct more errors with longer latency, allowing for efficient error correction by utilizing ECC concatenation and embedding FD decoders in memory devices and AD decoders in storage controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single ECC decoder is used, then device complexity is reduced, but correction capability and latency performance cannot be simultaneously optimized
Solution Approach 1:
The ECC decoder is segmented into two distinct decoders: a first decoder that performs initial error correction with lower complexity, and a second decoder that handles residual errors. This segmentation allows each decoder to be optimized for its specific function, achieving high correction capability without requiring a single overly complex decoder.
Solution Approach 2:
The patent introduces a hierarchical dimension to the decoder structure, organizing decoders in levels where the first decoder operates at a lower level for quick corrections, and the second decoder operates at a higher level for more complex error patterns. This dimensional organization resolves the contradiction by adding structural hierarchy rather than increasing flat complexity.
2Reliability
If a high correction capability ECC decoder is used, then error correction capability is improved, but access latency increases
Solution Approach 1:
The first decoder performs preliminary error correction before the second decoder operates. By correcting easily detectable errors in advance, the system reduces the workload for subsequent decoding stages, thereby reducing overall access latency while maintaining high correction capability.
Solution Approach 2:
The first decoder performs partial error correction, handling the most common and easily correctable error patterns. This partial action suffices for many cases, reducing average access latency, while the second decoder provides excessive correction capability for more difficult error patterns that require more time and resources.
3Loss of time
If a low latency ECC decoder is used, then access latency is reduced, but correction capability deteriorates
Solution Approach 1:
The decoder function is segmented into multiple specialized decoders, where the first decoder is optimized for low latency operations on common error patterns, and the second decoder provides enhanced correction capability for more complex errors. This segmentation allows the system to achieve low average latency while maintaining high overall correction capability.
Solution Approach 2:
The first decoder acts as an intermediary between the memory array and the second decoder. It performs initial error correction and passes only the residual errors to the second decoder, thereby mediating between the need for fast correction and the need for comprehensive error handling capability.
Data Source
AI summary
Apparatuses and methods related to correcting errors can include using fast decoding (FD) decoders and accurate decoding (AD) decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.