FD-SOI 3D Interconnect Layout for Source and Drain Access
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Solution Overview
Problem
Existing microelectronic devices with fully-depleted silicon-on-insulator (FD-SOI) transistors face challenges in efficiently accessing and connecting the source and drain, limiting further improvements in electrical access and performance.
Innovation Solution
The proposed microelectronic unit incorporates an epitaxial silicon layer with a buried oxide layer and ohmic contacts, along with dielectric layers and conductive elements, to enhance electrical access and connectivity between the source, drain, and external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive interconnects extend through numerous dielectric layers to access source and drain, then electrical connection is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar 2D interconnect routing to 3D vertical interconnect architecture. Conductive elements extend vertically through the thickness of the semiconductor substrate, enabling direct access to source and drain regions without traversing multiple horizontal dielectric layers. This dimensional change simplifies the interconnect structure while maintaining reliable electrical connection.
Solution Approach 2:
The invention extracts and removes portions of the bulk silicon substrate to create through-holes or recesses. This extraction enables direct vertical pathways for conductive elements to reach the source and drain regions, eliminating the need for complex lateral routing through numerous dielectric layers and reducing overall device complexity.
2Ease of manufacture
If conventional interconnect methods are used, then manufacturing process is established, but electrical access efficiency is limited
Solution Approach 1:
The patent performs preliminary substrate thinning and patterned removal of bulk silicon regions before forming the final interconnect structure. By pre-establishing vertical pathways and reducing substrate thickness in targeted areas, the manufacturing process is simplified and electrical access efficiency is enhanced without requiring complex subsequent processing steps.
3Reliability
If FD-SOI transistor structure is used, then device performance is improved, but access to source and drain becomes more challenging
Solution Approach 1:
The patent employs vertical 3D interconnect elements that extend through the thin FD-SOI substrate thickness, providing direct access to source and drain regions from the back surface. This vertical approach bypasses the limitations of lateral access in thin-film FD-SOI structures, making electrode formation and electrical contact significantly easier while preserving the high-performance characteristics of the FD-SOI transistor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves electrical access and connectivity, enabling more efficient operation of FD-SOI transistors and potentially enhancing the performance and reliability of microelectronic devices.
Implementation Method 1
The epitaxial silicon layer may be epitaxially grown over the buried oxide layer
Implementation Method 2
an ohmic contact extending through the buried oxide layer between the top and bottom oxide surfaces
Data Source
AI summary
A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.