3D FD-SOI Interconnect Layout for Source and Drain Access
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Solution Overview
Problem
Existing microelectronic devices with FD-SOI transistors face challenges in efficiently accessing and connecting the source and drain, limiting further improvements in transistor access.
Innovation Solution
The proposed microelectronic unit incorporates an epitaxial silicon layer with a buried oxide layer and ohmic contacts, along with dielectric layers and conductive elements, to enhance access and connection to the source and drain, allowing for improved electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive interconnects extend through numerous dielectric layers to access source and drain, then electrical connection is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar 2D interconnect routing to 3D vertical interconnect architecture. Conductive elements extend through the thickness of the semiconductor substrate, utilizing the third dimension (depth) to establish electrical connections between bond pads on the front surface and active circuitry on the back surface, thereby simplifying the interconnect structure while maintaining reliable electrical connection
2Ease of manufacture
If conventional interconnect methods are used, then manufacturing process is established, but access to source and drain becomes inefficient
Solution Approach 1:
The patent segments the interconnect function into distinct vertical components: front dielectric layers, conductive elements extending through the substrate, back dielectric layers, and bond pad structures. This segmentation allows each component to be optimized independently while maintaining overall manufacturing feasibility and improving transistor access efficiency through the vertical architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables more efficient electrical access and connection to the source and drain, potentially leading to improved performance and reliability of FD-SOI transistors.
Implementation Method 1
The epitaxial silicon layer may be epitaxially grown over the buried oxide layer
Implementation Method 2
an ohmic contact extending through the buried oxide layer between the top and bottom oxide surfaces
Implementation Method 3
one or more conductive elements extending through the one or more dielectric layers between the first and second dielectric surfaces
Data Source
AI summary
A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.