Back Biasing FD-SOI Circuit Block Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In 3D microelectronic circuit structures with stacked die, existing technologies face challenges in optimizing transistor performance across different regions due to variations in process parameters and functional requirements, leading to suboptimal operation and increased leakage.
Innovation Solution
Selective back biasing of transistors within the upper FD-SOI layer allows for independent adjustment of bias levels for different functional circuit blocks, compensating for process variations and optimizing performance without uniformly affecting the entire system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If uniform back biasing is applied to the entire upper FD-SOI layer, then leakage is reduced, but performance of different functional circuit blocks cannot be optimized independently
Solution Approach 1:
The upper FD-SOI layer is segmented into multiple independently biasable regions through separate back gate connections. Each functional circuit block (e.g., logic circuits, memory circuits, RF circuits) can be connected to its own back gate terminal, allowing independent threshold voltage control for each segment while maintaining overall leakage reduction across the entire layer.
Solution Approach 2:
Different back bias voltages are applied to different regions of the upper FD-SOI layer according to the specific performance requirements of each functional circuit block. High-performance blocks requiring speed can receive bias voltages that lower their threshold voltage, while blocks requiring low power consumption can receive bias voltages that raise their threshold voltage, achieving local optimization without affecting other regions.
2Loss of energy
If back bias voltage is increased to reduce leakage, then energy efficiency improves, but transistor switching speed decreases
Solution Approach 1:
The back bias voltage applied to each functional circuit block can be dynamically adjusted based on operational requirements. During active high-performance modes, bias voltages are tuned to optimize switching speed, while during idle or low-power modes, bias voltages are adjusted to maximize leakage reduction and energy efficiency, allowing the system to adapt to changing performance demands.
Solution Approach 2:
Different dynamic biasing strategies can be applied to different functional blocks simultaneously. Time-critical blocks such as processor units can maintain higher bias voltages for fast switching, while non-critical blocks such as cache memory can use lower bias voltages for energy savings, with each block's bias voltage independently controlled according to its specific performance-energy tradeoff requirements.
3Speed
If threshold voltage is decreased to improve transistor speed, then performance increases, but leakage increases
Solution Approach 1:
The upper FD-SOI layer is divided into multiple segments with independent back gate control, allowing different threshold voltages to be established in different regions. Speed-critical segments can be configured with lower threshold voltages through appropriate back bias voltages, while non-critical segments can maintain higher threshold voltages for low leakage, with each segment's threshold voltage independently optimized for its specific functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved performance and reduced leakage by tailoring bias levels to specific circuit blocks, enhancing operational efficiency and addressing process variations at a circuit block level.
Implementation Method 1
a bias voltage applied at the back side of the SOI substrate can be used for controlling the threshold voltage of the transistors built on the front side of the SOI substrate
Data Source
AI summary
A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the from surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.