FD-SOI Gate-All-Around Transistor Structure for Higher Drive Current
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Solution Overview
Problem
There is a need to improve transistor device structures to enhance electrostatic coupling, reduce parasitic capacitance, and increase drive current without increasing transistor size, as FinFETs and other existing technologies face limitations in scaling down while maintaining performance.
Innovation Solution
The development of a gate all-around (GAA) device with a fully-depleted silicon-on-insulator (FD-SOI) transistor structure, incorporating a buried dielectric isolation layer and FD-SOI channel beneath the gate, which includes a superlattice structure with alternating semiconductor layers and channel layers, and a metal gate surrounding the channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FinFET structure is used to increase drive current, then transistor speed improves, but device footprint increases
Solution Approach 1:
The patent transitions from planar 2D channel structure to 3D vertically-stacked channel structure. Multiple channel layers are stacked vertically above the substrate, enabling the gate to wrap around and control channels from multiple directions (front, back, and sides). This vertical stacking achieves higher drive current equivalent to much larger planar devices while occupying minimal footprint area.
Solution Approach 2:
The gate structure completely surrounds each channel layer in a nested configuration. The gate wraps around the channel from front and back surfaces, with dielectric layers providing isolation. This all-around gating structure enables maximum electrostatic control of the channel while maintaining compact device geometry.
2Area of stationary object
If transistor dimensions are scaled down to reduce size, then device density increases, but drive current decreases
Solution Approach 1:
Instead of scaling down planar dimensions which reduces drive current, the patent stacks multiple channels vertically. Each channel layer maintains sufficient cross-sectional area for adequate drive current, while the vertical stacking achieves high device density. The gate structure extends to wrap around all channels in the stack, providing uniform control across all dimensions.
Solution Approach 2:
The channel region is segmented into multiple discrete horizontal channel layers separated by dielectric isolation layers. Each channel layer can be independently controlled by the surrounding gate structure. This segmentation allows parallel conduction paths through multiple channels, achieving high total drive current while maintaining small lateral footprint.
3Ease of manufacture
If conventional transistor structures are used, then manufacturing is simpler, but electrostatic control is insufficient
Solution Approach 1:
The gate structure completely encloses each channel layer in a nested configuration, wrapping around front, back, and sides. Dielectric layers are nested between channel layers and around the gate structure. This all-around gating provides maximum electrostatic control with uniform field distribution, improving device reliability and performance.
Data Source
AI summary
Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric isolation layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric isolation layer has a thickness in a range of from 0 nm to 10 nm.