Selective Silicon Thinning for Mixed FD-SOI and PD-SOI Integration
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Solution Overview
Problem
Existing silicon-on-insulator (SOI) technologies face challenges in manufacturing both fully depleted (FD-SOI) and partially depleted (PD-SOI) devices on the same substrate due to differences in silicon thickness requirements, leading to increased complexity and cost, particularly in achieving optimal RF switch performance metrics like RON×COFF and threshold voltage control.
Innovation Solution
A method is developed to fabricate both PD-SOI and FD-SOI devices on the same semiconductor substrate by selectively thinning the silicon layer to appropriate thicknesses for each type, using shallow trench isolation (STI) regions to electrically isolate them, and employing common dopant implants for source/drain regions, allowing for the integration of PD-SOI devices in control circuits and FD-SOI devices in RF switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the silicon layer thickness is reduced to enable FD-SOI devices, then junction capacitance and floating body effects are reduced, but manufacturing complexity and cost increase due to tight thickness control requirements
Solution Approach 1:
The patent applies local quality by creating different silicon thickness regions within the same wafer - thinner regions (50-150 nm) for FD-SOI devices and thicker regions for PD-SOI devices. This allows each region to have the optimal thickness for its intended device type, achieving low junction capacitance in FD-SOI regions without requiring the entire wafer to meet tight thickness specifications.
Solution Approach 2:
The patent segments the wafer into multiple regions with different silicon thicknesses using selective thinning processes. By dividing the wafer into FD-SOI regions and PD-SOI regions, the manufacturing process can accommodate both device types with their respective thickness requirements, reducing overall manufacturing complexity while maintaining the benefits of thin silicon for FD-SOI devices.
2Reliability
If the silicon layer thickness is reduced to enable FD-SOI devices, then electrostatic control is improved, but threshold voltage variation increases due to trapped charge in the buried oxide layer
Solution Approach 1:
The patent creates local quality differences by providing thinner silicon regions for FD-SOI devices where improved electrostatic control is needed, while maintaining thicker regions for PD-SOI devices that are less sensitive to electrostatic control. This localized approach allows electrostatic control improvements only where required without propagating threshold voltage variation issues across the entire wafer.
3Ease of manufacture
If PD-SOI devices are used, then manufacturing is easier and cost is lower, but floating body effects cause body potential shifts that degrade performance
Solution Approach 1:
The patent applies local quality by placing FD-SOI devices with reduced floating body effects in specific regions where body potential stability is critical, while using PD-SOI devices in regions where manufacturing simplicity is more important. This allows the circuit to achieve overall reliability while maintaining manufacturing ease.
4Adaptability or versatility
If both FD-SOI and PD-SOI devices are fabricated on the same substrate, then integration is achieved, but process complexity increases due to different silicon thickness requirements
Solution Approach 1:
The patent segments the fabrication process into stages where a common thick silicon layer is first formed for both device types, then selective thinning is applied to create thinner regions for FD-SOI devices. This segmented approach allows both device types to be processed on the same substrate while minimizing process complexity by using a common starting layer.
Solution Approach 2:
The patent achieves universality by using a common thick silicon layer for both PD-SOI and FD-SOI device fabrication before selective thinning. This universal starting layer simplifies the overall process compared to using separate wafers, while the subsequent selective thinning enables both device types to coexist on the same substrate.
Data Source
AI summary
Methods for fabricating both PD-SOI devices and FD-SOI devices on the same semiconductor substrate are provided. The methods begin with a SOI wafer having a top silicon layer with a thickness appropriate for the fabrication of PD-SOI devices. During the fabrication process, portions of the top silicon layer, to be used for the fabrication of FD-SOI devices, are selectively thinned, so that a portion of the wafer has a top silicon thickness appropriate for FD-SOI devices. FD-SOI devices (e.g., RF switch transistors) are fabricated in the thinned portions of the top silicon layer, and PD-SOI devices (e.g., control transistors for the RF switch transistors) are fabricated in the non-thinned portions of the top silicon layer. Thus, both PD-SOI and FD-SOI devices can be combined within the same integrated circuit.