FD-SOI RF Substrate P-N Junction Formation by Thermal Diffusion
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Solution Overview
Problem
Fully-Depleted Silicon on Insulator (FD-SOI) structures used in radio frequency applications face electrical losses due to substrate compatibility issues with charge trapping layers, which hinder back bias voltage control and increase manufacturing costs through complex lithography and implantation steps for lateral P-N junction formation.
Innovation Solution
A method for manufacturing an FD-SOI type structure with a high resistivity substrate and a P-N junction formed by diffusing P-type dopants through an insulating layer, using a heat treatment process that eliminates the need for additional processing steps like localized implantation and mask deposition, allowing for controlled P-N junction formation at specific depths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If lateral PN junctions are formed by implantation with mask, then electrical losses in substrate are reduced, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent extracts the P-type dopant from the semiconductor layer and transports it through the BOX layer to the substrate, eliminating the need for separate implantation steps and masks. This extraction approach simplifies the manufacturing process while achieving the same electrical loss reduction effect.
Solution Approach 2:
The BOX layer acts as an intermediary medium that enables the transfer of P-type dopants from the semiconductor layer to the substrate. By using thermal diffusion through the BOX layer as a mediator, the patent avoids direct implantation into the substrate, thereby reducing process complexity.
2Loss of energy
If charge trapping layer is added to reduce substrate electrical losses, then RF performance improves, but back bias voltage control is hindered
Solution Approach 1:
The patent replaces the charge trapping layer approach with a P-N junction formed by P-type dopant diffusion. This substitution eliminates the interference with back bias voltage control while maintaining the ability to reduce substrate electrical losses through the lateral P-N junction structure.
3Loss of energy
If high resistivity substrate is used for RF applications, then electrical losses are reduced, but compatibility with back bias transistors is compromised
Solution Approach 1:
The patent applies local quality by forming P-type doped regions at specific locations in the substrate through dopant diffusion. This creates localized P-N junctions that reduce electrical losses while leaving other regions of the substrate suitable for back bias transistor operation, thereby maintaining versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances radio frequency performance by reducing parasitic electric fields and electrical losses, while simplifying the manufacturing process and reducing costs by eliminating the need for complex lithography and additional implantation steps.
Implementation Method 1
by the diffusion of P type dopants from the monocrystalline semiconductor layer through the electrically insulating layer in said substrate
Implementation Method 2
by the formation in said substrate of thermal donors by precipitation of the interstitial oxygen
Data Source
Figure 1~3
Figure 4~5B
Figure 5C~6B
AI summary
The invention relates to a method for manufacturing a semiconductor-on-insulator structure (10), comprising the following steps: - providing an FD-SOI substrate (1) comprising, successively from its base to its top: a monocrystalline substrate (2) having an electrical resistivity of between 500 Ω.cm and 30 kΩ.cm, an interstitial oxygen content (Oi) of between 20 and 40 old ppma, and having an N- or P-type doping, an electrically insulating layer (3) having a thickness of between 20 nm and 400 nm, a monocrystalline layer (4) having a P-type doping, - heat-treating the FD-SOI substrate (1) at a temperature greater than or equal to 1175°C for a time greater than or equal to 1 hour in order to form a P-N junction (5) in the substrate. The invention also relates to such a semiconductor-on-insulator structure.