FD-SOI Transistor Cell With Common Well Biasing
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Solution Overview
Problem
In electronic devices using fully depleted silicon-on-insulator (FD-SOI) technology, existing designs face challenges in efficiently balancing the threshold voltages, on-state currents, off-state currents, and switching speeds of nMOS and pMOS transistors, which affects power consumption and operational efficiency at low supply voltages.
Innovation Solution
The integration of transistors in FD-SOI technology with a common semiconductor well and buried control electrode allows for all transistors to be biased with a single adjustable voltage, enabling balanced threshold voltages, currents, and switching speeds, while reducing the device footprint through shared components and isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate biasing voltages are used for nMOS and pMOS transistors, then independent control of threshold voltages is possible, but device complexity and footprint increase
Solution Approach 1:
The patent merges the biasing control of nMOS and pMOS transistors by connecting both substrate contacts to a common well structure. This single well receives a unified biasing voltage that simultaneously controls both transistor types, eliminating the need for separate biasing circuits while maintaining threshold voltage control capability.
Solution Approach 2:
The common well structure serves multiple functions: it acts as the substrate for both nMOS and pMOS transistors, provides a unified biasing voltage distribution network, and enables simultaneous control of both transistor threshold voltages through a single control node, demonstrating multi-functionality that reduces overall device complexity.
2Reliability
If transistors are separated with isolation regions, then transistor performance is optimized, but device footprint increases
Solution Approach 1:
The patent merges the substrate structures of nMOS and pMOS transistors into a single common well, eliminating the need for separate isolation regions between transistors. The well itself provides the necessary electrical isolation and performance optimization while reducing the overall area required for transistor placement.
Solution Approach 2:
The common well structure provides localized electrical properties at different regions within the well, allowing nMOS and pMOS transistors to maintain their specific performance characteristics while sharing the same substrate infrastructure. The well can be doped or structured differently in local regions to optimize each transistor type's performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient power management by balancing transistor parameters, reducing power consumption, and minimizing device size, thereby enhancing operational efficiency and flexibility in electronic device design.
Implementation Method 1
an insulating region located between the well and the silicon layer
Implementation Method 2
bias the substrates of all of the transistors of the cell with the same biasing voltage... increase the threshold voltage of the pMOS transistor and simultaneously decrease the threshold voltage of the nMOS transistor
Data Source
AI summary
An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.