FDMDA Operator for Simultaneous Double Multiplication and Addition
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Solution Overview
Problem
Current processor cores are limited in performing combined operations involving multiple multiplications and additions with more than three operands, requiring additional instructions and register identifiers, which hampers efficient evaluation of polynomials, matrix multiplications, and complex number operations.
Innovation Solution
The introduction of a processor core instruction set with a fused double multiplication and addition (FDMDA) operator that combines two multiplications and two additions using three register references, allowing for simultaneous calculation and addition of products, enabling efficient evaluation of polynomials, matrix products, and complex number operations without losing accuracy through rounding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor core uses traditional FMA operator with three operands, then the instruction set can be kept simple with three register identifiers, but it cannot efficiently perform combined operations with more than three operands requiring additional instructions
Solution Approach 1:
The patent merges multiple FMA operations into a single hardware operator that can process more than three operands simultaneously. The operator is extended to accept multiple multiplication pairs and accumulation terms, combining what would traditionally require multiple sequential FMA instructions into one unified operation that executes in a single cycle.
Solution Approach 2:
The enhanced operator is designed to be universal, capable of handling various combined operations including polynomial evaluation, matrix multiplications, and complex number operations. By making the operator multi-functional, the processor can efficiently execute diverse computational tasks without requiring separate specialized hardware for each operation type.
2Measurement precision
If the processor evaluates polynomials or performs matrix multiplications with multiple operands, then computational accuracy may be maintained, but the number of instructions required increases
Solution Approach 1:
The operator is designed to perform all necessary multiplications and additions in a single unified operation, eliminating the need for intermediate rounding steps that would occur with sequential FMA instructions. By computing all products and accumulations simultaneously in one operation, the processor maintains full precision throughout the calculation without premature rounding errors.
3Productivity
If the hardware operator performs multiple multiplications and additions simultaneously, then productivity improves, but the device complexity increases
Solution Approach 1:
The enhanced operator is segmented into distinct functional units that handle different aspects of the computation independently. Multiple multiplication units process different operand pairs simultaneously, while accumulation units handle the addition of products to running totals. This segmentation allows parallel execution of multiple operations while keeping each individual processing unit relatively simple and manageable.
Data Source
AI summary
A method of processing data by a processor, the method comprising the steps of: receiving, by the processor, an instruction including an operator code associated with three register references designating registers configured to contain pairs of multiplication operands, an addition operand, and a result register configured to receive an operator result, the operator code designating an operator configured to compute products of the pairs of multiplication operands and add the products with the addition operand; decoding the instruction by an instruction decoder of the processor, to determine the operator to be executed, and the registers containing the operands to be supplied to the operator and the result of the operator; actuating the operator by an arithmetic circuit of the processor, consuming the operands in the registers designated by the register references; and storing the result of the operator in the designated result register.