FDP-Compliant SSD RAID Region Alignment for Garbage Collection
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Solution Overview
Problem
Conventional memory sub-systems face inefficiencies in FDP systems due to misalignment of error correction parity information stripes across memory components with varying region sizes, impacting garbage collection and overall performance.
Innovation Solution
A memory controller ensures sufficient deletion of error correction parity information stripes to create at least one completely empty region in each memory component, independent of physical layer dependencies, by computing the quantity based on region sizes and deleting multiple stripes as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If error correction parity information stripes are deleted in conventional memory sub-systems, then space is freed for garbage collection, but complete region deletion cannot be ensured across memory components with varying region sizes, leading to misalignment and performance degradation
Solution Approach 1:
The memory controller performs preliminary computation to determine the exact number of parity stripes to delete based on the largest region size across all memory components. This preliminary calculation ensures that when deletion occurs, complete region alignment is achieved without requiring trial-and-error or iterative processes, thereby preventing misalignment issues while maximizing space recovery for garbage collection.
Solution Approach 2:
The system dynamically adjusts the deletion quantity parameter of parity stripes based on the identified largest region size. By changing the deletion parameter from a fixed conventional approach to a dynamic calculation that incorporates region size information, the system ensures complete region deletion across all memory components while optimizing space recovery for garbage collection operations.
2Reliability
If the number of parity stripes to delete is computed based on the largest region size, then complete region deletion is ensured, but the deletion process becomes more complex and time-consuming
Solution Approach 1:
The memory controller creates a virtual copy of the region size information to perform calculations independently. By working with a copied representation of region sizes rather than directly manipulating the physical memory structure, the system simplifies the computation process while ensuring accurate determination of the largest region size for proper parity stripe deletion alignment.
Solution Approach 2:
The deletion computation process is segmented into distinct steps: identifying the largest region size, calculating the required number of parity stripes to delete, and then executing the deletion. This segmentation breaks down the complex task into manageable operations, reducing overall computational complexity while maintaining complete region alignment assurance.
3Reliability
If multiple parity stripes are deleted to ensure complete region deletion, then region alignment is improved, but the operation time and productivity are reduced
Solution Approach 1:
The system performs preliminary identification and calculation of the exact number of parity stripes to delete before initiating the deletion process. This preliminary action eliminates the need for iterative or trial deletion processes, ensuring that the correct number of stripes is removed in a single operation to achieve complete region alignment, thereby minimizing operation time while maintaining garbage collection efficiency.
Solution Approach 2:
The deletion process is designed to continuously and efficiently remove the calculated number of parity stripes without interruption or unnecessary delays. By ensuring the correct quantity is deleted based on the largest region size, the system maintains continuous useful action throughout the deletion process, avoiding both under-deletion (which would cause alignment failures) and over-deletion (which would waste time and reduce productivity).
Data Source
AI summary
The disclosure configures a memory sub-system controller to perform Redundant Array of Independent Disks (RAID) stripe deletion based on physical region size. The controller stores a set of data across a plurality of memory components, a first of the plurality of components being configured to store data in a first set of regions, a second of the plurality of components being configured to store data in a second set of regions. The controller generates a plurality of error correction parity information stripes for multiple collections of the set of data and computes a quantity of the plurality of error correction parity information stripes to delete based on sizes of each region in the first and second sets of regions. The controller deletes one or more of the plurality of error correction parity information stripes based on the computed quantity.