FDSOI Inverter Back Gate Voltage Tolerance
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Solution Overview
Problem
Conventional integrated circuit inverters at technology nodes below 32 nm face challenges in withstanding high voltages due to thin gate oxides, requiring additional protection circuits that increase area consumption and vulnerability to voltage spikes despite these protections.
Innovation Solution
The implementation of FDSOI technology with back gates separated by a thicker buried oxide layer, allowing higher voltage tolerance without additional protection circuits, as the back gates act as primary gates and can withstand higher voltages due to the thicker dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bulk technology is used at 32 nm node or smaller, then the gate oxide thickness must be reduced to achieve higher integration, but the maximum voltage that can be applied across transistor terminals is limited to 2 V or less
Solution Approach 1:
The patent changes the physical parameters of the transistor structure by transitioning from bulk technology to FDSOI (Fully Depleted Silicon-On-Insulator) technology. This enables the use of thicker gate oxides (improving manufacturing precision and reducing leakage) while simultaneously allowing higher voltage operation (improving reliability) through the unique SOI device physics and thicker buried oxide layer that prevents punch-through effects.
Solution Approach 2:
The patent employs a composite structure consisting of a thin semiconductor layer (2-10 nm) deposited on a thick buried oxide layer (50-200 nm), which itself sits on a substrate. This composite material architecture enables the gate oxide to be thicker than in bulk technology while maintaining effective channel control, thus resolving the contradiction between thin oxide requirements for scaling and thick oxide requirements for voltage tolerance.
2Reliability
If protection circuits are added to protect MOS transistors from high voltage, then voltage overload protection is improved, but the circuit area increases and vulnerability to voltage spikes remains
Solution Approach 1:
The patent extracts and removes the protection circuits from the design by fundamentally changing the transistor technology to FDSOI, which inherently tolerates higher voltages without requiring external protection. This eliminates the need for additional protection transistors and circuitry, thereby reducing circuit area while maintaining robustness against voltage spikes through the intrinsic voltage tolerance of the SOI devices.
3Reliability
If FDSOI technology with back gates is used, then voltage tolerance is improved and area consumption is reduced, but the device complexity increases due to dual gate structure
Solution Approach 1:
The patent applies multi-functionality to the back gate structure. The back gate serves multiple purposes: it provides additional voltage tolerance, enables independent control of the channel, allows for threshold voltage tuning, and can function as a second control terminal for analog applications. This multi-functional use of the back gate justifies the increased structural complexity by delivering enhanced performance and versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces area consumption and enhances voltage tolerance, enabling the inverter to operate reliably at higher voltages without the need for additional protection circuits, thus improving the robustness and efficiency of the integrated circuit design.
Implementation Method 1
The back gates are formed in a second semiconductor layer separated from the first semiconductor layer by buried oxide layer. The buried oxide layers thicker than the gate dielectric. The buried oxide layer serves as a second gate dielectric separating the back gates from the respective channel regions.
Data Source
AI summary
A CMOS device is formed in an FDSOI integrated circuit die. By retrieving the MOS functionality for gate voltage levels higher than its stress limits, second gate availability in these devices is being used, and hence removing the additional circuitry that would have been used for protecting the devices from such stress. Implementation in an inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.