FDSOI pMOS Device Segmentation for Mobility
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Solution Overview
Problem
In p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) devices, the increase in the width of the active channel region decreases mobility and performance, as the current flow region is reduced due to gaps between adjacent narrow-width regions not contributing to drive current.
Innovation Solution
Forming gaps in the channel silicon germanium (SiGe) area to increase strain and mobility by epitaxially growing a doped SiGe layer on a buried oxide layer, with the gaps extending into the SiGe layer to a depth less than or equal to its thickness, and using techniques like sidewall image transfer or directed self-assembly to create striped structures that change the strain from biaxial to uniaxial, facilitating improved current flow and reducing source-drain resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the width of the SiGe active channel region is increased, then the current flow area is increased, but carrier mobility decreases and performance deteriorates
Solution Approach 1:
The SiGe active channel region is segmented into multiple narrow-width regions separated by gaps. This segmentation allows the structure to achieve both increased effective current flow area through multiple parallel channels and maintained high carrier mobility in each narrow channel, resolving the contradiction between area and mobility
Solution Approach 2:
Different regions of the device are given different properties: the channel regions are made narrow to maximize carrier mobility, while the overall device width is increased by adding multiple such regions. The gaps between regions are strategically positioned to maintain electrical isolation while allowing strain penetration, creating local quality variations that satisfy both requirements
2Reliability
If the silicon layer is converted to silicon germanium (SiGe) to increase compressive strain, then majority carrier (hole) mobility increases, but the width of the SiGe active channel region must be decreased which reduces current flow area
Solution Approach 1:
The device is segmented into multiple narrow SiGe channels separated by gaps. Each narrow channel maintains high carrier mobility due to its narrow width and compressive strain, while the multiplication of channels compensates for the reduced individual channel area, achieving both high mobility and sufficient total current flow area
Solution Approach 2:
The invention transitions from a single wide channel (one-dimensional approach) to multiple narrow channels arranged in parallel (multi-dimensional approach). This dimensional change allows the device to achieve both high mobility (through narrow channel width) and high current capacity (through increased number of channels) simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and device performance by increasing the current flow area and reducing resistance, while maintaining a narrow-width layout to improve drive current without decreasing performance.
Implementation Method 1
epitaxially growing a doped SiGe layer on a buried oxide layer
Implementation Method 2
increase the strain of the compressively strained SiGe increases majority carrier (hole) mobility
Data Source
AI summary
A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.