Raised Source/Drain Recessing in FDSOI to Cut Parasitic Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased parasitic resistance and manufacturing defects due to coefficient of thermal expansion mismatches between silicon layers and buried oxide layers, which affect electrical performance and reliability.
Innovation Solution
The formation of fully depleted silicon on insulator (FDSOI) transistors with raised source/drain regions, where the top silicon layer is etched to create deeper recesses using a fluorine-ozone mixture process, reducing parasitic resistance and supporting subsequent processing steps while maintaining a sufficient thickness to prevent substrate cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the top silicon layer is etched deeper to extend source/drain regions, then parasitic resistance is reduced, but the structural support and reliability may be compromised
Solution Approach 1:
The patent applies local quality by creating recesses only in specific regions where source/drain extensions are needed, while maintaining the full thickness of the top silicon layer in other areas. This allows the source/drain regions to extend deeper into the substrate locally to reduce parasitic resistance, while the remaining top silicon layer provides structural support elsewhere. The selective etching of recesses rather than uniform thinning enables this localized modification of material properties.
Solution Approach 2:
The patent resolves the contradiction by transitioning from a two-dimensional planar source/drain structure to a three-dimensional structure with vertical recesses. By etching recesses that extend downward into the substrate while maintaining lateral dimensions, the source/drain regions gain additional vertical extent, increasing the effective contact area with the channel and reducing parasitic resistance without compromising the overall structural integrity provided by the remaining top silicon layer.
2Productivity
If minimum feature sizes are reduced for higher integration density, then more components can be integrated, but parasitic resistance and leakage currents increase
Solution Approach 1:
The patent addresses the electrical performance degradation from scaled dimensions by adding a vertical dimension to the source/drain structure. The recesses extend downward into the substrate, creating a three-dimensional structure that increases the effective source/drain contact area with the channel. This vertical extension compensates for the reduced lateral dimensions, maintaining electrical performance despite smaller minimum feature sizes and enabling continued integration density improvements.
Solution Approach 2:
The patent changes the geometric parameters of the source/drain regions by creating recesses with specific depth and width dimensions. By controlling the recess depth to extend below the gate structure while maintaining appropriate width, the effective source/drain area is increased. This parameter modification reduces parasitic resistance and leakage currents, allowing the device to maintain electrical performance as minimum feature sizes are reduced for higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical performance by reducing parasitic resistance and minimizing manufacturing defects like substrate cracking, achieving a performance boost of 6% or more in nMOS transistors and maintaining structural integrity during processing.
Implementation Method 1
etching recesses in the top silicon layer using a fluorine-ozone mixture process
Data Source
AI summary
A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.